1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Brcmstb PCIe Host Controller
8
9 maintainers:
10 - Jim Quinlan <james.quinlan@broadcom.com>
11
12 properties:
13 compatible:
14 items:
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
20 - brcm,bcm7278-pcie # Broadcom 7278 Arm
21 - brcm,bcm7425-pcie # Broadcom 7425 MIPs
22 - brcm,bcm7435-pcie # Broadcom 7435 MIPs
23 - brcm,bcm7445-pcie # Broadcom 7445 Arm
24 - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5
25
26 reg:
27 maxItems: 1
28
29 interrupts:
30 minItems: 1
31 items:
32 - description: PCIe host controller
33 - description: builtin MSI controller
34
35 interrupt-names:
36 minItems: 1
37 items:
38 - const: pcie
39 - const: msi
40
41 ranges:
42 minItems: 1
43 maxItems: 4
44
45 dma-ranges:
46 minItems: 1
47 maxItems: 6
48
49 clocks:
50 maxItems: 1
51
52 clock-names:
53 items:
54 - const: sw_pcie
55
56 msi-controller:
57 description: Identifies the node as an MSI controller.
58
59 msi-parent:
60 description: MSI controller the device is capable of using.
61
62 brcm,enable-ssc:
63 description: Indicates usage of spread-spectrum clocking.
64 type: boolean
65
66 aspm-no-l0s: true
67
68 brcm,clkreq-mode:
69 description: A string that determines the operating
70 clkreq mode of the PCIe RC HW with respect to controlling the refclk
71 signal. There are three different modes -- "safe", which drives the
72 refclk signal unconditionally and will work for all devices but does
73 not provide any power savings; "no-l1ss" -- which provides Clock
74 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
75 power savings. If the downstream device connected to the RC is L1SS
76 capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
77 potentially hanging the system; "default" -- which provides L0s, L1,
78 and L1SS, but not compliant to provide Clock Power Management;
79 specifically, may not be able to meet the T_CLRon max timing of 400ns
80 as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI
81 Express Mini CEM 2.1 specification. This situation is atypical and
82 should happen only with older devices.
83 $ref: /schemas/types.yaml#/definitions/string
84 enum: [ safe, no-l1ss, default ]
85
86 brcm,scb-sizes:
87 description: u64 giving the 64bit PCIe memory
88 viewport size of a memory controller. There may be up to
89 three controllers, and each size must be a power of two
90 with a size greater or equal to the amount of memory the
91 controller supports. Note that each memory controller
92 may have two component regions -- base and extended -- so
93 this information cannot be deduced from the dma-ranges.
94 $ref: /schemas/types.yaml#/definitions/uint64-array
95 items:
96 minItems: 1
97 maxItems: 3
98
99 resets:
100 minItems: 1
101 maxItems: 3
102
103 reset-names:
104 minItems: 1
105 maxItems: 3
106
107 required:
108 - compatible
109 - reg
110 - ranges
111 - dma-ranges
112 - "#interrupt-cells"
113 - interrupts
114 - interrupt-names
115 - interrupt-map-mask
116 - interrupt-map
117 - msi-controller
118
119 allOf:
120 - $ref: /schemas/pci/pci-host-bridge.yaml#
121 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
122 - if:
123 properties:
124 compatible:
125 contains:
126 const: brcm,bcm4908-pcie
127 then:
128 properties:
129 resets:
130 maxItems: 1
131
132 reset-names:
133 items:
134 - const: perst
135
136 required:
137 - resets
138 - reset-names
139 - if:
140 properties:
141 compatible:
142 contains:
143 const: brcm,bcm7216-pcie
144 then:
145 properties:
146 resets:
147 maxItems: 1
148
149 reset-names:
150 items:
151 - const: rescal
152
153 required:
154 - resets
155 - reset-names
156
157 - if:
158 properties:
159 compatible:
160 contains:
161 const: brcm,bcm7712-pcie
162 then:
163 properties:
164 resets:
165 minItems: 3
166 maxItems: 3
167
168 reset-names:
169 items:
170 - const: rescal
171 - const: bridge
172 - const: swinit
173
174 required:
175 - resets
176 - reset-names
177
178 unevaluatedProperties: false
179
180 examples:
181 - |
182 #include <dt-bindings/interrupt-controller/irq.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
184
185 scb {
186 #address-cells = <2>;
187 #size-cells = <1>;
188 pcie0: pcie@7d500000 {
189 compatible = "brcm,bcm2711-pcie";
190 reg = <0x0 0x7d500000 0x9310>;
191 device_type = "pci";
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-names = "pcie", "msi";
198 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
203
204 msi-parent = <&pcie0>;
205 msi-controller;
206 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
207 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
208 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
209 brcm,enable-ssc;
210 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
211
212 /* PCIe bridge, Root Port */
213 pci@0,0 {
214 #address-cells = <3>;
215 #size-cells = <2>;
216 reg = <0x0 0x0 0x0 0x0 0x0>;
217 compatible = "pciclass,0604";
218 device_type = "pci";
219 vpcie3v3-supply = <&vreg7>;
220 ranges;
221
222 /* PCIe endpoint */
223 pci-ep@0,0 {
224 assigned-addresses =
225 <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
226 reg = <0x0 0x0 0x0 0x0 0x0>;
227 compatible = "pci14e4,1688";
228 };
229 };
230 };
231 };
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