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Linux/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Intel Keem Bay PCIe controller Root Complex mode
  8 
  9 maintainers:
 10   - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
 11   - Srikanth Thokala <srikanth.thokala@intel.com>
 12 
 13 allOf:
 14   - $ref: /schemas/pci/pci-host-bridge.yaml#
 15 
 16 properties:
 17   compatible:
 18     const: intel,keembay-pcie
 19 
 20   ranges:
 21     maxItems: 1
 22 
 23   reset-gpios:
 24     maxItems: 1
 25 
 26   reg:
 27     maxItems: 4
 28 
 29   reg-names:
 30     items:
 31       - const: dbi
 32       - const: atu
 33       - const: config
 34       - const: apb
 35 
 36   clocks:
 37     maxItems: 2
 38 
 39   clock-names:
 40     items:
 41       - const: master
 42       - const: aux
 43 
 44   interrupts:
 45     maxItems: 3
 46 
 47   interrupt-names:
 48     items:
 49       - const: pcie
 50       - const: pcie_ev
 51       - const: pcie_err
 52 
 53   num-lanes:
 54     description: Number of lanes to use.
 55     enum: [ 1, 2 ]
 56 
 57 required:
 58   - compatible
 59   - reg
 60   - reg-names
 61   - ranges
 62   - clocks
 63   - clock-names
 64   - interrupts
 65   - interrupt-names
 66   - reset-gpios
 67 
 68 unevaluatedProperties: false
 69 
 70 examples:
 71   - |
 72     #include <dt-bindings/interrupt-controller/arm-gic.h>
 73     #include <dt-bindings/interrupt-controller/irq.h>
 74     #include <dt-bindings/gpio/gpio.h>
 75     #define KEEM_BAY_A53_PCIE
 76     #define KEEM_BAY_A53_AUX_PCIE
 77     pcie@37000000 {
 78           compatible = "intel,keembay-pcie";
 79           reg = <0x37000000 0x00001000>,
 80                 <0x37300000 0x00001000>,
 81                 <0x36e00000 0x00200000>,
 82                 <0x37800000 0x00000200>;
 83           reg-names = "dbi", "atu", "config", "apb";
 84           #address-cells = <3>;
 85           #size-cells = <2>;
 86           device_type = "pci";
 87           ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
 88           interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 89                        <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 90                        <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 91           interrupt-names = "pcie", "pcie_ev", "pcie_err";
 92           clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
 93                    <&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
 94           clock-names = "master", "aux";
 95           reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
 96           num-lanes = <2>;
 97     };

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