1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek MT7621 PCIe controller
8
9 maintainers:
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12 description: |+
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
15
16 MT7621 PCIe HOST Topology
17
18 .-------.
19 | |
20 | CPU |
21 | |
22 '-------'
23 |
24 |
25 |
26 v
27 .------------------.
28 .-----------| HOST/PCI Bridge |------------.
29 | '------------------' | Type1
30 BUS0 | | | Access
31 v v v On Bus0
32 .-------------. .-------------. .-------------.
33 | VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
34 | BUS0 | | BUS0 | | BUS0 |
35 | DEV0 | | DEV1 | | DEV2 |
36 '-------------' '-------------' '-------------'
37 Type0 | Type0 | Type0 |
38 Access BUS1 | Access BUS2| Access BUS3|
39 On Bus1 v On Bus2 v On Bus3 v
40 .----------. .----------. .----------.
41 | Device 0 | | Device 0 | | Device 0 |
42 | Func 0 | | Func 0 | | Func 0 |
43 '----------' '----------' '----------'
44
45 allOf:
46 - $ref: /schemas/pci/pci-host-bridge.yaml#
47
48 properties:
49 compatible:
50 const: mediatek,mt7621-pci
51
52 reg:
53 items:
54 - description: host-pci bridge registers
55 - description: pcie port 0 RC control registers
56 - description: pcie port 1 RC control registers
57 - description: pcie port 2 RC control registers
58
59 ranges:
60 maxItems: 2
61
62 patternProperties:
63 '^pcie@[0-2],0$':
64 type: object
65 $ref: /schemas/pci/pci-pci-bridge.yaml#
66
67 properties:
68 reg:
69 maxItems: 1
70
71 resets:
72 maxItems: 1
73
74 clocks:
75 maxItems: 1
76
77 phys:
78 maxItems: 1
79
80 phy-names:
81 pattern: '^pcie-phy[0-2]$'
82
83 required:
84 - "#interrupt-cells"
85 - interrupt-map-mask
86 - interrupt-map
87 - resets
88 - clocks
89 - phys
90 - phy-names
91 - ranges
92
93 unevaluatedProperties: false
94
95 required:
96 - compatible
97 - reg
98 - ranges
99 - "#interrupt-cells"
100 - interrupt-map-mask
101 - interrupt-map
102 - reset-gpios
103
104 unevaluatedProperties: false
105
106 examples:
107 - |
108 #include <dt-bindings/gpio/gpio.h>
109 #include <dt-bindings/interrupt-controller/mips-gic.h>
110
111 pcie: pcie@1e140000 {
112 compatible = "mediatek,mt7621-pci";
113 reg = <0x1e140000 0x100>,
114 <0x1e142000 0x100>,
115 <0x1e143000 0x100>,
116 <0x1e144000 0x100>;
117
118 #address-cells = <3>;
119 #size-cells = <2>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pcie_pins>;
122 device_type = "pci";
123 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
124 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
125 #interrupt-cells = <1>;
126 interrupt-map-mask = <0xF800 0 0 0>;
127 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
129 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
130 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
131
132 pcie@0,0 {
133 reg = <0x0000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 device_type = "pci";
137 #interrupt-cells = <1>;
138 interrupt-map-mask = <0 0 0 0>;
139 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
140 resets = <&rstctrl 24>;
141 clocks = <&clkctrl 24>;
142 phys = <&pcie0_phy 1>;
143 phy-names = "pcie-phy0";
144 ranges;
145 };
146
147 pcie@1,0 {
148 reg = <0x0800 0 0 0 0>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 device_type = "pci";
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
155 resets = <&rstctrl 25>;
156 clocks = <&clkctrl 25>;
157 phys = <&pcie0_phy 1>;
158 phy-names = "pcie-phy1";
159 ranges;
160 };
161
162 pcie@2,0 {
163 reg = <0x1000 0 0 0 0>;
164 #address-cells = <3>;
165 #size-cells = <2>;
166 device_type = "pci";
167 #interrupt-cells = <1>;
168 interrupt-map-mask = <0 0 0 0>;
169 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
170 resets = <&rstctrl 26>;
171 clocks = <&clkctrl 26>;
172 phys = <&pcie2_phy 0>;
173 phy-names = "pcie-phy2";
174 ranges;
175 };
176 };
177 ...
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