1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Microchip PCIe Root Port Bridge Controller
8
9 maintainers:
10 - Daire McNamara <daire.mcnamara@microchip.com>
11
12 allOf:
13 - $ref: plda,xpressrich3-axi-common.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
16 properties:
17 compatible:
18 const: microchip,pcie-host-1.0 # PolarFire
19
20 clocks:
21 description:
22 Fabric Interface Controllers, FICs, are the interface between the FPGA
23 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
24 one from each side of the interface. The "FIC clocks" described by this
25 property are on the core complex side & communication through a FIC is not
26 possible unless it's corresponding clock is enabled. A clock must be
27 enabled for each of the interfaces the root port is connected through.
28 This could in theory be all 4 interfaces, one interface or any combination
29 in between.
30 minItems: 1
31 items:
32 - description: FIC0's clock
33 - description: FIC1's clock
34 - description: FIC2's clock
35 - description: FIC3's clock
36
37 clock-names:
38 description:
39 As any FIC connection combination is possible, the names should match the
40 order in the clocks property and take the form "ficN" where N is a number
41 0-3
42 minItems: 1
43 maxItems: 4
44 items:
45 pattern: '^fic[0-3]$'
46
47 ranges:
48 minItems: 1
49 maxItems: 3
50
51 dma-ranges:
52 minItems: 1
53 maxItems: 6
54
55 unevaluatedProperties: false
56
57 examples:
58 - |
59 soc {
60 #address-cells = <2>;
61 #size-cells = <2>;
62 pcie0: pcie@2030000000 {
63 compatible = "microchip,pcie-host-1.0";
64 reg = <0x0 0x70000000 0x0 0x08000000>,
65 <0x0 0x43000000 0x0 0x00010000>;
66 reg-names = "cfg", "apb";
67 device_type = "pci";
68 #address-cells = <3>;
69 #size-cells = <2>;
70 #interrupt-cells = <1>;
71 interrupts = <119>;
72 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
73 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
74 <0 0 0 2 &pcie_intc0 1>,
75 <0 0 0 3 &pcie_intc0 2>,
76 <0 0 0 4 &pcie_intc0 3>;
77 interrupt-parent = <&plic0>;
78 msi-parent = <&pcie0>;
79 msi-controller;
80 bus-range = <0x00 0x7f>;
81 ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
82 pcie_intc0: interrupt-controller {
83 #address-cells = <0>;
84 #interrupt-cells = <1>;
85 interrupt-controller;
86 };
87 };
88 };
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