1 NVIDIA Tegra PCIe controller
2
3 Required properties:
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
12 for Tegra186.
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
16 - reg-names: Must include the following entries:
17 "pads": PADS registers
18 "afi": AFI registers
19 "cs": configuration space region
20 - interrupts: A list of interrupt outputs of the controller. Must contain an
21 entry for each entry in the interrupt-names property.
22 - interrupt-names: Must include the following entries:
23 "intr": The Tegra interrupt that is asserted for controller interrupts
24 "msi": The Tegra interrupt that is asserted when an MSI is received
25 - bus-range: Range of bus numbers associated with this controller
26 - #address-cells: Address representation for root ports (must be 3)
27 - cell 0 specifies the bus and device numbers of the root port:
28 [23:16]: bus number
29 [15:11]: device number
30 - cell 1 denotes the upper 32 address bits and should be 0
31 - cell 2 contains the lower 32 address bits and is used to translate to the
32 CPU address space
33 - #size-cells: Size representation for root ports (must be 2)
34 - ranges: Describes the translation of addresses for root ports and standard
35 PCI regions. The entries must be 6 cells each, where the first three cells
36 correspond to the address as described for the #address-cells property
37 above, the fourth cell is the physical CPU address to translate to and the
38 fifth and six cells are as described for the #size-cells property above.
39 - The first two entries are expected to translate the addresses for the root
40 port registers, which are referenced by the assigned-addresses property of
41 the root port nodes (see below).
42 - The remaining entries setup the mapping for the standard I/O, memory and
43 prefetchable PCI regions. The first cell determines the type of region
44 that is setup:
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
48 Please refer to the standard PCI bus binding document for a more detailed
49 explanation.
50 - #interrupt-cells: Size representation for interrupts (must be 1)
51 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 Please refer to the standard PCI bus binding document for a more detailed
53 explanation.
54 - clocks: Must contain an entry for each entry in clock-names.
55 See ../clocks/clock-bindings.txt for details.
56 - clock-names: Must include the following entries:
57 - pex
58 - afi
59 - pll_e
60 - cml (not required for Tegra20)
61 - resets: Must contain an entry for each entry in reset-names.
62 See ../reset/reset.txt for details.
63 - reset-names: Must include the following entries:
64 - pex
65 - afi
66 - pcie_x
67
68 Optional properties:
69 - pinctrl-names: A list of pinctrl state names. Must contain the following
70 entries:
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
73 - pinctrl-0: phandle for the default/active state of pin configurations.
74 - pinctrl-1: phandle for the idle state of pin configurations.
75
76 Required properties on Tegra124 and later (deprecated):
77 - phys: Must contain an entry for each entry in phy-names.
78 - phy-names: Must include the following entries:
79 - pcie
80
81 These properties are deprecated in favour of per-lane PHYs define in each of
82 the root ports (see below).
83
84 Power supplies for Tegra20:
85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
88 supply 1.05 V.
89 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
90 supply 1.05 V.
91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
92
93 Power supplies for Tegra30:
94 - Required:
95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
96 supply 1.05 V.
97 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
98 supply 1.05 V.
99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
100 supply 1.8 V.
101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
102 Must supply 3.3 V.
103 - Optional:
104 - If lanes 0 to 3 are used:
105 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
106 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
107 - If lanes 4 or 5 are used:
108 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
109 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
110
111 Power supplies for Tegra124:
112 - Required:
113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
114 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
115 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
116 Must supply 3.3 V.
117 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
118 supply 2.8-3.3 V.
119
120 Power supplies for Tegra210:
121 - Required:
122 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
123 clocks. Must supply 1.8 V.
124 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
125 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
126 supply 1.8 V.
127
128 Power supplies for Tegra186:
129 - Required:
130 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
131 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
132 supply 1.8 V.
133 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
134 Must supply 1.8 V.
135 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
136 supply 1.8 V.
137
138 Root ports are defined as subnodes of the PCIe controller node.
139
140 Required properties:
141 - device_type: Must be "pci"
142 - assigned-addresses: Address and size of the port configuration registers
143 - reg: PCI bus address of the root port
144 - #address-cells: Must be 3
145 - #size-cells: Must be 2
146 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
147 property is sufficient.
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
149 are:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
152
153 Required properties for Tegra124 and later:
154 - phys: Must contain an phandle to a PHY for each entry in phy-names.
155 - phy-names: Must include an entry for each active lane. Note that the number
156 of entries does not have to (though usually will) be equal to the specified
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
159
160 Examples:
161 =========
162
163 Tegra20:
164 --------
165
166 SoC DTSI:
167
168 pcie-controller@80003000 {
169 compatible = "nvidia,tegra20-pcie";
170 device_type = "pci";
171 reg = <0x80003000 0x00000800 /* PADS registers */
172 0x80003800 0x00000200 /* AFI registers */
173 0x90000000 0x10000000>; /* configuration space */
174 reg-names = "pads", "afi", "cs";
175 interrupts = <0 98 0x04 /* controller interrupt */
176 0 99 0x04>; /* MSI interrupt */
177 interrupt-names = "intr", "msi";
178
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
182
183 bus-range = <0x00 0xff>;
184 #address-cells = <3>;
185 #size-cells = <2>;
186
187 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
188 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
189 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
190 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
191 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
192
193 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
194 clock-names = "pex", "afi", "pll_e";
195 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
196 reset-names = "pex", "afi", "pcie_x";
197 status = "disabled";
198
199 pci@1,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
202 reg = <0x000800 0 0 0 0>;
203 status = "disabled";
204
205 #address-cells = <3>;
206 #size-cells = <2>;
207
208 ranges;
209
210 nvidia,num-lanes = <2>;
211 };
212
213 pci@2,0 {
214 device_type = "pci";
215 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
216 reg = <0x001000 0 0 0 0>;
217 status = "disabled";
218
219 #address-cells = <3>;
220 #size-cells = <2>;
221
222 ranges;
223
224 nvidia,num-lanes = <2>;
225 };
226 };
227
228 Board DTS:
229
230 pcie-controller@80003000 {
231 status = "okay";
232
233 vdd-supply = <&pci_vdd_reg>;
234 pex-clk-supply = <&pci_clk_reg>;
235
236 /* root port 00:01.0 */
237 pci@1,0 {
238 status = "okay";
239
240 /* bridge 01:00.0 (optional) */
241 pci@0,0 {
242 reg = <0x010000 0 0 0 0>;
243
244 #address-cells = <3>;
245 #size-cells = <2>;
246
247 device_type = "pci";
248
249 /* endpoint 02:00.0 */
250 pci@0,0 {
251 reg = <0x020000 0 0 0 0>;
252 };
253 };
254 };
255 };
256
257 Note that devices on the PCI bus are dynamically discovered using PCI's bus
258 enumeration and therefore don't need corresponding device nodes in DT. However
259 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
260 device nodes need to be added in order to allow the bus' children to be
261 instantiated at the proper location in the operating system's device tree (as
262 illustrated by the optional nodes in the example above).
263
264 Tegra30:
265 --------
266
267 SoC DTSI:
268
269 pcie-controller@3000 {
270 compatible = "nvidia,tegra30-pcie";
271 device_type = "pci";
272 reg = <0x00003000 0x00000800 /* PADS registers */
273 0x00003800 0x00000200 /* AFI registers */
274 0x10000000 0x10000000>; /* configuration space */
275 reg-names = "pads", "afi", "cs";
276 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
277 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
278 interrupt-names = "intr", "msi";
279
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
283
284 bus-range = <0x00 0xff>;
285 #address-cells = <3>;
286 #size-cells = <2>;
287
288 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
289 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
290 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
291 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
292 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
293 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
294
295 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
296 <&tegra_car TEGRA30_CLK_AFI>,
297 <&tegra_car TEGRA30_CLK_PLL_E>,
298 <&tegra_car TEGRA30_CLK_CML0>;
299 clock-names = "pex", "afi", "pll_e", "cml";
300 resets = <&tegra_car 70>,
301 <&tegra_car 72>,
302 <&tegra_car 74>;
303 reset-names = "pex", "afi", "pcie_x";
304 status = "disabled";
305
306 pci@1,0 {
307 device_type = "pci";
308 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
309 reg = <0x000800 0 0 0 0>;
310 status = "disabled";
311
312 #address-cells = <3>;
313 #size-cells = <2>;
314 ranges;
315
316 nvidia,num-lanes = <2>;
317 };
318
319 pci@2,0 {
320 device_type = "pci";
321 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
322 reg = <0x001000 0 0 0 0>;
323 status = "disabled";
324
325 #address-cells = <3>;
326 #size-cells = <2>;
327 ranges;
328
329 nvidia,num-lanes = <2>;
330 };
331
332 pci@3,0 {
333 device_type = "pci";
334 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
335 reg = <0x001800 0 0 0 0>;
336 status = "disabled";
337
338 #address-cells = <3>;
339 #size-cells = <2>;
340 ranges;
341
342 nvidia,num-lanes = <2>;
343 };
344 };
345
346 Board DTS:
347
348 pcie-controller@3000 {
349 status = "okay";
350
351 avdd-pexa-supply = <&ldo1_reg>;
352 vdd-pexa-supply = <&ldo1_reg>;
353 avdd-pexb-supply = <&ldo1_reg>;
354 vdd-pexb-supply = <&ldo1_reg>;
355 avdd-pex-pll-supply = <&ldo1_reg>;
356 avdd-plle-supply = <&ldo1_reg>;
357 vddio-pex-ctl-supply = <&sys_3v3_reg>;
358 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
359
360 pci@1,0 {
361 status = "okay";
362 };
363
364 pci@3,0 {
365 status = "okay";
366 };
367 };
368
369 Tegra124:
370 ---------
371
372 SoC DTSI:
373
374 pcie-controller@1003000 {
375 compatible = "nvidia,tegra124-pcie";
376 device_type = "pci";
377 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
378 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
379 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
380 reg-names = "pads", "afi", "cs";
381 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
382 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
383 interrupt-names = "intr", "msi";
384
385 #interrupt-cells = <1>;
386 interrupt-map-mask = <0 0 0 0>;
387 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
388
389 bus-range = <0x00 0xff>;
390 #address-cells = <3>;
391 #size-cells = <2>;
392
393 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
394 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
395 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
396 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
397 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
398
399 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
400 <&tegra_car TEGRA124_CLK_AFI>,
401 <&tegra_car TEGRA124_CLK_PLL_E>,
402 <&tegra_car TEGRA124_CLK_CML0>;
403 clock-names = "pex", "afi", "pll_e", "cml";
404 resets = <&tegra_car 70>,
405 <&tegra_car 72>,
406 <&tegra_car 74>;
407 reset-names = "pex", "afi", "pcie_x";
408 status = "disabled";
409
410 pci@1,0 {
411 device_type = "pci";
412 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
413 reg = <0x000800 0 0 0 0>;
414 status = "disabled";
415
416 #address-cells = <3>;
417 #size-cells = <2>;
418 ranges;
419
420 nvidia,num-lanes = <2>;
421 };
422
423 pci@2,0 {
424 device_type = "pci";
425 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
426 reg = <0x001000 0 0 0 0>;
427 status = "disabled";
428
429 #address-cells = <3>;
430 #size-cells = <2>;
431 ranges;
432
433 nvidia,num-lanes = <1>;
434 };
435 };
436
437 Board DTS:
438
439 pcie-controller@1003000 {
440 status = "okay";
441
442 avddio-pex-supply = <&vdd_1v05_run>;
443 dvddio-pex-supply = <&vdd_1v05_run>;
444 avdd-pex-pll-supply = <&vdd_1v05_run>;
445 hvdd-pex-supply = <&vdd_3v3_lp0>;
446 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
447 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
448 avdd-pll-erefe-supply = <&avdd_1v05_run>;
449
450 /* Mini PCIe */
451 pci@1,0 {
452 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
453 phy-names = "pcie-0";
454 status = "okay";
455 };
456
457 /* Gigabit Ethernet */
458 pci@2,0 {
459 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
460 phy-names = "pcie-0";
461 status = "okay";
462 };
463 };
464
465 Tegra210:
466 ---------
467
468 SoC DTSI:
469
470 pcie-controller@1003000 {
471 compatible = "nvidia,tegra210-pcie";
472 device_type = "pci";
473 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
474 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
475 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
476 reg-names = "pads", "afi", "cs";
477 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
478 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
479 interrupt-names = "intr", "msi";
480
481 #interrupt-cells = <1>;
482 interrupt-map-mask = <0 0 0 0>;
483 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
484
485 bus-range = <0x00 0xff>;
486 #address-cells = <3>;
487 #size-cells = <2>;
488
489 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
490 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
491 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
492 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
493 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
494
495 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
496 <&tegra_car TEGRA210_CLK_AFI>,
497 <&tegra_car TEGRA210_CLK_PLL_E>,
498 <&tegra_car TEGRA210_CLK_CML0>;
499 clock-names = "pex", "afi", "pll_e", "cml";
500 resets = <&tegra_car 70>,
501 <&tegra_car 72>,
502 <&tegra_car 74>;
503 reset-names = "pex", "afi", "pcie_x";
504 status = "disabled";
505
506 pci@1,0 {
507 device_type = "pci";
508 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
509 reg = <0x000800 0 0 0 0>;
510 status = "disabled";
511
512 #address-cells = <3>;
513 #size-cells = <2>;
514 ranges;
515
516 nvidia,num-lanes = <4>;
517 };
518
519 pci@2,0 {
520 device_type = "pci";
521 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
522 reg = <0x001000 0 0 0 0>;
523 status = "disabled";
524
525 #address-cells = <3>;
526 #size-cells = <2>;
527 ranges;
528
529 nvidia,num-lanes = <1>;
530 };
531 };
532
533 Board DTS:
534
535 pcie-controller@1003000 {
536 status = "okay";
537
538 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
539 hvddio-pex-supply = <&vdd_1v8>;
540 dvddio-pex-supply = <&vdd_pex_1v05>;
541 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
542 hvdd-pex-pll-e-supply = <&vdd_1v8>;
543 vddio-pex-ctl-supply = <&vdd_1v8>;
544
545 pci@1,0 {
546 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
547 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
548 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
549 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
550 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
551 status = "okay";
552 };
553
554 pci@2,0 {
555 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
556 phy-names = "pcie-0";
557 status = "okay";
558 };
559 };
560
561 Tegra186:
562 ---------
563
564 SoC DTSI:
565
566 pcie@10003000 {
567 compatible = "nvidia,tegra186-pcie";
568 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
569 device_type = "pci";
570 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
571 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
572 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
573 reg-names = "pads", "afi", "cs";
574
575 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
576 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
577 interrupt-names = "intr", "msi";
578
579 #interrupt-cells = <1>;
580 interrupt-map-mask = <0 0 0 0>;
581 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
582
583 bus-range = <0x00 0xff>;
584 #address-cells = <3>;
585 #size-cells = <2>;
586
587 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
588 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
589 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
590 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
591 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
592 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
593
594 clocks = <&bpmp TEGRA186_CLK_AFI>,
595 <&bpmp TEGRA186_CLK_PCIE>,
596 <&bpmp TEGRA186_CLK_PLLE>;
597 clock-names = "afi", "pex", "pll_e";
598
599 resets = <&bpmp TEGRA186_RESET_AFI>,
600 <&bpmp TEGRA186_RESET_PCIE>,
601 <&bpmp TEGRA186_RESET_PCIEXCLK>;
602 reset-names = "afi", "pex", "pcie_x";
603
604 status = "disabled";
605
606 pci@1,0 {
607 device_type = "pci";
608 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
609 reg = <0x000800 0 0 0 0>;
610 status = "disabled";
611
612 #address-cells = <3>;
613 #size-cells = <2>;
614 ranges;
615
616 nvidia,num-lanes = <2>;
617 };
618
619 pci@2,0 {
620 device_type = "pci";
621 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
622 reg = <0x001000 0 0 0 0>;
623 status = "disabled";
624
625 #address-cells = <3>;
626 #size-cells = <2>;
627 ranges;
628
629 nvidia,num-lanes = <1>;
630 };
631
632 pci@3,0 {
633 device_type = "pci";
634 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
635 reg = <0x001800 0 0 0 0>;
636 status = "disabled";
637
638 #address-cells = <3>;
639 #size-cells = <2>;
640 ranges;
641
642 nvidia,num-lanes = <1>;
643 };
644 };
645
646 Board DTS:
647
648 pcie@10003000 {
649 status = "okay";
650
651 dvdd-pex-supply = <&vdd_pex>;
652 hvdd-pex-pll-supply = <&vdd_1v8>;
653 hvdd-pex-supply = <&vdd_1v8>;
654 vddio-pexctl-aud-supply = <&vdd_1v8>;
655
656 pci@1,0 {
657 nvidia,num-lanes = <4>;
658 status = "okay";
659 };
660
661 pci@2,0 {
662 nvidia,num-lanes = <0>;
663 status = "disabled";
664 };
665
666 pci@3,0 {
667 nvidia,num-lanes = <1>;
668 status = "disabled";
669 };
670 };
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