1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm PCIe Endpoint Controller
8
9 maintainers:
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12 properties:
13 compatible:
14 oneOf:
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
20 - const: qcom,sdx65-pcie-ep
21 - const: qcom,sdx55-pcie-ep
22
23 reg:
24 minItems: 6
25 items:
26 - description: Qualcomm-specific PARF configuration registers
27 - description: DesignWare PCIe registers
28 - description: External local bus interface registers
29 - description: Address Translation Unit (ATU) registers
30 - description: Memory region used to map remote RC address space
31 - description: BAR memory region
32 - description: DMA register space
33
34 reg-names:
35 minItems: 6
36 items:
37 - const: parf
38 - const: dbi
39 - const: elbi
40 - const: atu
41 - const: addr_space
42 - const: mmio
43 - const: dma
44
45 clocks:
46 minItems: 5
47 maxItems: 8
48
49 clock-names:
50 minItems: 5
51 maxItems: 8
52
53 qcom,perst-regs:
54 description: Reference to a syscon representing TCSR followed by the two
55 offsets within syscon for Perst enable and Perst separation
56 enable registers
57 $ref: /schemas/types.yaml#/definitions/phandle-array
58 items:
59 - items:
60 - description: Syscon to TCSR system registers
61 - description: Perst enable offset
62 - description: Perst separation enable offset
63
64 interrupts:
65 minItems: 2
66 items:
67 - description: PCIe Global interrupt
68 - description: PCIe Doorbell interrupt
69 - description: DMA interrupt
70
71 interrupt-names:
72 minItems: 2
73 items:
74 - const: global
75 - const: doorbell
76 - const: dma
77
78 reset-gpios:
79 description: GPIO used as PERST# input signal
80 maxItems: 1
81
82 wake-gpios:
83 description: GPIO used as WAKE# output signal
84 maxItems: 1
85
86 interconnects:
87 maxItems: 2
88
89 interconnect-names:
90 items:
91 - const: pcie-mem
92 - const: cpu-pcie
93
94 resets:
95 maxItems: 1
96
97 reset-names:
98 const: core
99
100 power-domains:
101 maxItems: 1
102
103 phys:
104 maxItems: 1
105
106 phy-names:
107 const: pciephy
108
109 num-lanes:
110 default: 2
111
112 required:
113 - compatible
114 - reg
115 - reg-names
116 - clocks
117 - clock-names
118 - interrupts
119 - interrupt-names
120 - reset-gpios
121 - interconnects
122 - interconnect-names
123 - resets
124 - reset-names
125 - power-domains
126
127 allOf:
128 - $ref: pci-ep.yaml#
129 - if:
130 properties:
131 compatible:
132 contains:
133 enum:
134 - qcom,sdx55-pcie-ep
135 then:
136 properties:
137 reg:
138 maxItems: 6
139 reg-names:
140 maxItems: 6
141 clocks:
142 items:
143 - description: PCIe Auxiliary clock
144 - description: PCIe CFG AHB clock
145 - description: PCIe Master AXI clock
146 - description: PCIe Slave AXI clock
147 - description: PCIe Slave Q2A AXI clock
148 - description: PCIe Sleep clock
149 - description: PCIe Reference clock
150 clock-names:
151 items:
152 - const: aux
153 - const: cfg
154 - const: bus_master
155 - const: bus_slave
156 - const: slave_q2a
157 - const: sleep
158 - const: ref
159 interrupts:
160 maxItems: 2
161 interrupt-names:
162 maxItems: 2
163
164 - if:
165 properties:
166 compatible:
167 contains:
168 enum:
169 - qcom,sm8450-pcie-ep
170 then:
171 properties:
172 reg:
173 maxItems: 6
174 reg-names:
175 maxItems: 6
176 clocks:
177 items:
178 - description: PCIe Auxiliary clock
179 - description: PCIe CFG AHB clock
180 - description: PCIe Master AXI clock
181 - description: PCIe Slave AXI clock
182 - description: PCIe Slave Q2A AXI clock
183 - description: PCIe Reference clock
184 - description: PCIe DDRSS SF TBU clock
185 - description: PCIe AGGRE NOC AXI clock
186 clock-names:
187 items:
188 - const: aux
189 - const: cfg
190 - const: bus_master
191 - const: bus_slave
192 - const: slave_q2a
193 - const: ref
194 - const: ddrss_sf_tbu
195 - const: aggre_noc_axi
196 interrupts:
197 maxItems: 2
198 interrupt-names:
199 maxItems: 2
200
201 - if:
202 properties:
203 compatible:
204 contains:
205 enum:
206 - qcom,sa8775p-pcie-ep
207 then:
208 properties:
209 reg:
210 minItems: 7
211 maxItems: 7
212 reg-names:
213 minItems: 7
214 maxItems: 7
215 clocks:
216 items:
217 - description: PCIe Auxiliary clock
218 - description: PCIe CFG AHB clock
219 - description: PCIe Master AXI clock
220 - description: PCIe Slave AXI clock
221 - description: PCIe Slave Q2A AXI clock
222 clock-names:
223 items:
224 - const: aux
225 - const: cfg
226 - const: bus_master
227 - const: bus_slave
228 - const: slave_q2a
229 interrupts:
230 minItems: 3
231 maxItems: 3
232 interrupt-names:
233 minItems: 3
234 maxItems: 3
235
236 unevaluatedProperties: false
237
238 examples:
239 - |
240 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
241 #include <dt-bindings/gpio/gpio.h>
242 #include <dt-bindings/interconnect/qcom,sdx55.h>
243 #include <dt-bindings/interrupt-controller/arm-gic.h>
244
245 pcie_ep: pcie-ep@1c00000 {
246 compatible = "qcom,sdx55-pcie-ep";
247 reg = <0x01c00000 0x3000>,
248 <0x40000000 0xf1d>,
249 <0x40000f20 0xc8>,
250 <0x40001000 0x1000>,
251 <0x40002000 0x1000>,
252 <0x01c03000 0x3000>;
253 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
254 "mmio";
255
256 clocks = <&gcc GCC_PCIE_AUX_CLK>,
257 <&gcc GCC_PCIE_CFG_AHB_CLK>,
258 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
259 <&gcc GCC_PCIE_SLV_AXI_CLK>,
260 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
261 <&gcc GCC_PCIE_SLEEP_CLK>,
262 <&gcc GCC_PCIE_0_CLKREF_CLK>;
263 clock-names = "aux", "cfg", "bus_master", "bus_slave",
264 "slave_q2a", "sleep", "ref";
265
266 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
267
268 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-names = "global", "doorbell";
271 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
272 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
273 interconnect-names = "pcie-mem", "cpu-pcie";
274 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
275 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
276 resets = <&gcc GCC_PCIE_BCR>;
277 reset-names = "core";
278 power-domains = <&gcc PCIE_GDSC>;
279 phys = <&pcie0_lane>;
280 phy-names = "pciephy";
281 max-link-speed = <3>;
282 num-lanes = <2>;
283 linux,pci-domain = <0>;
284 };
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