1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SC7280 PCI Express Root Complex
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13 description:
14 Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
16
17 properties:
18 compatible:
19 const: qcom,pcie-sc7280
20
21 reg:
22 minItems: 5
23 maxItems: 6
24
25 reg-names:
26 minItems: 5
27 items:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
30 - const: elbi # External local bus interface registers
31 - const: atu # ATU address space
32 - const: config # PCIe configuration space
33 - const: mhi # MHI registers
34
35 clocks:
36 minItems: 13
37 maxItems: 13
38
39 clock-names:
40 items:
41 - const: pipe # PIPE clock
42 - const: pipe_mux # PIPE MUX
43 - const: phy_pipe # PIPE output clock
44 - const: ref # REFERENCE clock
45 - const: aux # Auxiliary clock
46 - const: cfg # Configuration clock
47 - const: bus_master # Master AXI clock
48 - const: bus_slave # Slave AXI clock
49 - const: slave_q2a # Slave Q2A clock
50 - const: tbu # PCIe TBU clock
51 - const: ddrss_sf_tbu # PCIe SF TBU clock
52 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
53 - const: aggre1 # Aggre NoC PCIe1 AXI clock
54
55 interrupts:
56 minItems: 8
57 maxItems: 8
58
59 interrupt-names:
60 items:
61 - const: msi0
62 - const: msi1
63 - const: msi2
64 - const: msi3
65 - const: msi4
66 - const: msi5
67 - const: msi6
68 - const: msi7
69
70 resets:
71 maxItems: 1
72
73 reset-names:
74 items:
75 - const: pci
76
77 allOf:
78 - $ref: qcom,pcie-common.yaml#
79
80 unevaluatedProperties: false
81
82 examples:
83 - |
84 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
85 #include <dt-bindings/clock/qcom,rpmh.h>
86 #include <dt-bindings/gpio/gpio.h>
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
88
89 soc {
90 #address-cells = <2>;
91 #size-cells = <2>;
92
93 pcie@1c08000 {
94 compatible = "qcom,pcie-sc7280";
95 reg = <0 0x01c08000 0 0x3000>,
96 <0 0x40000000 0 0xf1d>,
97 <0 0x40000f20 0 0xa8>,
98 <0 0x40001000 0 0x1000>,
99 <0 0x40100000 0 0x100000>;
100 reg-names = "parf", "dbi", "elbi", "atu", "config";
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
102 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
103
104 bus-range = <0x00 0xff>;
105 device_type = "pci";
106 linux,pci-domain = <1>;
107 num-lanes = <2>;
108
109 #address-cells = <3>;
110 #size-cells = <2>;
111
112 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
113 assigned-clock-rates = <19200000>;
114
115 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
116 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
117 <&pcie1_phy>,
118 <&rpmhcc RPMH_CXO_CLK>,
119 <&gcc GCC_PCIE_1_AUX_CLK>,
120 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
121 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
122 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
123 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
124 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
125 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
126 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
127 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
128
129 clock-names = "pipe",
130 "pipe_mux",
131 "phy_pipe",
132 "ref",
133 "aux",
134 "cfg",
135 "bus_master",
136 "bus_slave",
137 "slave_q2a",
138 "tbu",
139 "ddrss_sf_tbu",
140 "aggre0",
141 "aggre1";
142
143 dma-coherent;
144
145 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-names = "msi0", "msi1", "msi2", "msi3",
154 "msi4", "msi5", "msi6", "msi7";
155 #interrupt-cells = <1>;
156 interrupt-map-mask = <0 0 0 0x7>;
157 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
158 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
159 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
160 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
161
162 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
163 <0x100 &apps_smmu 0x1c81 0x1>;
164
165 phys = <&pcie1_phy>;
166 phy-names = "pciephy";
167
168 pinctrl-names = "default";
169 pinctrl-0 = <&pcie1_clkreq_n>;
170
171 power-domains = <&gcc GCC_PCIE_1_GDSC>;
172
173 resets = <&gcc GCC_PCIE_1_BCR>;
174 reset-names = "pci";
175
176 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
177 vddpe-3v3-supply = <&pp3300_ssd>;
178 };
179 };
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