1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM8150 PCI Express Root Complex
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13 description:
14 Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
16
17 properties:
18 compatible:
19 const: qcom,pcie-sm8150
20
21 reg:
22 minItems: 5
23 maxItems: 6
24
25 reg-names:
26 minItems: 5
27 items:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
30 - const: elbi # External local bus interface registers
31 - const: atu # ATU address space
32 - const: config # PCIe configuration space
33 - const: mhi # MHI registers
34
35 clocks:
36 minItems: 8
37 maxItems: 8
38
39 clock-names:
40 items:
41 - const: pipe # PIPE clock
42 - const: aux # Auxiliary clock
43 - const: cfg # Configuration clock
44 - const: bus_master # Master AXI clock
45 - const: bus_slave # Slave AXI clock
46 - const: slave_q2a # Slave Q2A clock
47 - const: tbu # PCIe TBU clock
48 - const: ref # REFERENCE clock
49
50 interrupts:
51 minItems: 8
52 maxItems: 8
53
54 interrupt-names:
55 items:
56 - const: msi0
57 - const: msi1
58 - const: msi2
59 - const: msi3
60 - const: msi4
61 - const: msi5
62 - const: msi6
63 - const: msi7
64
65 resets:
66 maxItems: 1
67
68 reset-names:
69 items:
70 - const: pci
71
72 allOf:
73 - $ref: qcom,pcie-common.yaml#
74
75 unevaluatedProperties: false
76
77 examples:
78 - |
79 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/gpio/gpio.h>
82 #include <dt-bindings/interconnect/qcom,sm8150.h>
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
84
85 soc {
86 #address-cells = <2>;
87 #size-cells = <2>;
88 pcie@1c00000 {
89 compatible = "qcom,pcie-sm8150";
90 reg = <0 0x01c00000 0 0x3000>,
91 <0 0x60000000 0 0xf1d>,
92 <0 0x60000f20 0 0xa8>,
93 <0 0x60001000 0 0x1000>,
94 <0 0x60100000 0 0x100000>;
95 reg-names = "parf", "dbi", "elbi", "atu", "config";
96 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
97 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
98
99 bus-range = <0x00 0xff>;
100 device_type = "pci";
101 linux,pci-domain = <0>;
102 num-lanes = <1>;
103
104 #address-cells = <3>;
105 #size-cells = <2>;
106
107 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
108 <&gcc GCC_PCIE_0_AUX_CLK>,
109 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
110 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
111 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
112 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
113 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
114 <&rpmhcc RPMH_CXO_CLK>;
115 clock-names = "pipe",
116 "aux",
117 "cfg",
118 "bus_master",
119 "bus_slave",
120 "slave_q2a",
121 "tbu",
122 "ref";
123
124 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-names = "msi0", "msi1", "msi2", "msi3",
133 "msi4", "msi5", "msi6", "msi7";
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 0x7>;
136 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
137 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
138 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
139 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
140
141 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
142 <0x100 &apps_smmu 0x1d81 0x1>;
143
144 phys = <&pcie0_phy>;
145 phy-names = "pciephy";
146
147 pinctrl-0 = <&pcie0_default_state>;
148 pinctrl-names = "default";
149
150 power-domains = <&gcc PCIE_0_GDSC>;
151
152 resets = <&gcc GCC_PCIE_0_BCR>;
153 reset-names = "pci";
154
155 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
156 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
157 };
158 };
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