1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM8450 PCI Express Root Complex
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13 description:
14 Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
16
17 properties:
18 compatible:
19 enum:
20 - qcom,pcie-sm8450-pcie0
21 - qcom,pcie-sm8450-pcie1
22
23 reg:
24 minItems: 5
25 maxItems: 6
26
27 reg-names:
28 minItems: 5
29 items:
30 - const: parf # Qualcomm specific registers
31 - const: dbi # DesignWare PCIe registers
32 - const: elbi # External local bus interface registers
33 - const: atu # ATU address space
34 - const: config # PCIe configuration space
35 - const: mhi # MHI registers
36
37 clocks:
38 minItems: 11
39 maxItems: 12
40
41 clock-names:
42 minItems: 11
43 items:
44 - const: pipe # PIPE clock
45 - const: pipe_mux # PIPE MUX
46 - const: phy_pipe # PIPE output clock
47 - const: ref # REFERENCE clock
48 - const: aux # Auxiliary clock
49 - const: cfg # Configuration clock
50 - const: bus_master # Master AXI clock
51 - const: bus_slave # Slave AXI clock
52 - const: slave_q2a # Slave Q2A clock
53 - const: ddrss_sf_tbu # PCIe SF TBU clock
54 - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
55 - const: aggre1 # Aggre NoC PCIe1 AXI clock
56
57 interrupts:
58 minItems: 9
59 maxItems: 9
60
61 interrupt-names:
62 items:
63 - const: msi0
64 - const: msi1
65 - const: msi2
66 - const: msi3
67 - const: msi4
68 - const: msi5
69 - const: msi6
70 - const: msi7
71 - const: global
72
73 operating-points-v2: true
74 opp-table:
75 type: object
76
77 resets:
78 maxItems: 1
79
80 reset-names:
81 items:
82 - const: pci
83
84 allOf:
85 - $ref: qcom,pcie-common.yaml#
86
87 unevaluatedProperties: false
88
89 examples:
90 - |
91 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
92 #include <dt-bindings/clock/qcom,rpmh.h>
93 #include <dt-bindings/gpio/gpio.h>
94 #include <dt-bindings/interconnect/qcom,sm8450.h>
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96
97 soc {
98 #address-cells = <2>;
99 #size-cells = <2>;
100
101 pcie@1c00000 {
102 compatible = "qcom,pcie-sm8450-pcie0";
103 reg = <0 0x01c00000 0 0x3000>,
104 <0 0x60000000 0 0xf1d>,
105 <0 0x60000f20 0 0xa8>,
106 <0 0x60001000 0 0x1000>,
107 <0 0x60100000 0 0x100000>;
108 reg-names = "parf", "dbi", "elbi", "atu", "config";
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
111
112 bus-range = <0x00 0xff>;
113 device_type = "pci";
114 linux,pci-domain = <0>;
115 max-link-speed = <2>;
116 num-lanes = <1>;
117
118 #address-cells = <3>;
119 #size-cells = <2>;
120
121 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
122 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
123 <&pcie0_phy>,
124 <&rpmhcc RPMH_CXO_CLK>,
125 <&gcc GCC_PCIE_0_AUX_CLK>,
126 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
127 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
128 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
129 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
130 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
131 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
132 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
133 clock-names = "pipe",
134 "pipe_mux",
135 "phy_pipe",
136 "ref",
137 "aux",
138 "cfg",
139 "bus_master",
140 "bus_slave",
141 "slave_q2a",
142 "ddrss_sf_tbu",
143 "aggre0",
144 "aggre1";
145
146 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-names = "msi0", "msi1", "msi2", "msi3",
156 "msi4", "msi5", "msi6", "msi7", "global";
157 #interrupt-cells = <1>;
158 interrupt-map-mask = <0 0 0 0x7>;
159 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
160 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
161 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
162 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
163 msi-map = <0x0 &gic_its 0x5981 0x1>,
164 <0x100 &gic_its 0x5980 0x1>;
165 msi-map-mask = <0xff00>;
166
167 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
168 <0x100 &apps_smmu 0x1c01 0x1>;
169
170 phys = <&pcie0_phy>;
171 phy-names = "pciephy";
172
173 pinctrl-0 = <&pcie0_default_state>;
174 pinctrl-names = "default";
175
176 power-domains = <&gcc PCIE_0_GDSC>;
177
178 resets = <&gcc GCC_PCIE_0_BCR>;
179 reset-names = "pci";
180
181 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
182 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
183 };
184 };
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