1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm X1E80100 PCI Express Root Complex
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13 description:
14 Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
16
17 properties:
18 compatible:
19 const: qcom,pcie-x1e80100
20
21 reg:
22 minItems: 6
23 maxItems: 6
24
25 reg-names:
26 items:
27 - const: parf # Qualcomm specific registers
28 - const: dbi # DesignWare PCIe registers
29 - const: elbi # External local bus interface registers
30 - const: atu # ATU address space
31 - const: config # PCIe configuration space
32 - const: mhi # MHI registers
33
34 clocks:
35 minItems: 7
36 maxItems: 7
37
38 clock-names:
39 items:
40 - const: aux # Auxiliary clock
41 - const: cfg # Configuration clock
42 - const: bus_master # Master AXI clock
43 - const: bus_slave # Slave AXI clock
44 - const: slave_q2a # Slave Q2A clock
45 - const: noc_aggr # Aggre NoC PCIe AXI clock
46 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
47
48 interrupts:
49 minItems: 8
50 maxItems: 8
51
52 interrupt-names:
53 items:
54 - const: msi0
55 - const: msi1
56 - const: msi2
57 - const: msi3
58 - const: msi4
59 - const: msi5
60 - const: msi6
61 - const: msi7
62
63 resets:
64 minItems: 1
65 maxItems: 2
66
67 reset-names:
68 minItems: 1
69 items:
70 - const: pci # PCIe core reset
71 - const: link_down # PCIe link down reset
72
73 allOf:
74 - $ref: qcom,pcie-common.yaml#
75
76 unevaluatedProperties: false
77
78 examples:
79 - |
80 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
81 #include <dt-bindings/gpio/gpio.h>
82 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
84
85 soc {
86 #address-cells = <2>;
87 #size-cells = <2>;
88
89 pcie@1c08000 {
90 compatible = "qcom,pcie-x1e80100";
91 reg = <0 0x01c08000 0 0x3000>,
92 <0 0x7c000000 0 0xf1d>,
93 <0 0x7c000f40 0 0xa8>,
94 <0 0x7c001000 0 0x1000>,
95 <0 0x7c100000 0 0x100000>,
96 <0 0x01c0b000 0 0x1000>;
97 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
99 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
100
101 bus-range = <0x00 0xff>;
102 device_type = "pci";
103 linux,pci-domain = <0>;
104 num-lanes = <2>;
105
106 #address-cells = <3>;
107 #size-cells = <2>;
108
109 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
110 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
111 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
112 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
113 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
114 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
115 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
116 clock-names = "aux",
117 "cfg",
118 "bus_master",
119 "bus_slave",
120 "slave_q2a",
121 "noc_aggr",
122 "cnoc_sf_axi";
123
124 dma-coherent;
125
126 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "msi0", "msi1", "msi2", "msi3",
135 "msi4", "msi5", "msi6", "msi7";
136 #interrupt-cells = <1>;
137 interrupt-map-mask = <0 0 0 0x7>;
138 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
139 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
140 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
141 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
142
143 interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
144 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
145 interconnect-names = "pcie-mem", "cpu-pcie";
146
147 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
148 <0x100 &apps_smmu 0x1401 0x1>;
149
150 phys = <&pcie4_phy>;
151 phy-names = "pciephy";
152
153 pinctrl-0 = <&pcie0_default_state>;
154 pinctrl-names = "default";
155
156 power-domains = <&gcc GCC_PCIE_4_GDSC>;
157
158 resets = <&gcc GCC_PCIE_4_BCR>;
159 reset-names = "pci";
160
161 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
162 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
163 };
164 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.