1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas AHB to PCI bridge
8
9 maintainers:
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
12
13 description: |
14 This is the bridge used internally to connect the USB controllers to the
15 AHB. There is one bridge instance per USB port connected to the internal
16 OHCI and EHCI controllers.
17
18 properties:
19 compatible:
20 oneOf:
21 - items:
22 - enum:
23 - renesas,pci-r8a7742 # RZ/G1H
24 - renesas,pci-r8a7743 # RZ/G1M
25 - renesas,pci-r8a7744 # RZ/G1N
26 - renesas,pci-r8a7745 # RZ/G1E
27 - renesas,pci-r8a7790 # R-Car H2
28 - renesas,pci-r8a7791 # R-Car M2-W
29 - renesas,pci-r8a7793 # R-Car M2-N
30 - renesas,pci-r8a7794 # R-Car E2
31 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - items:
33 - enum:
34 - renesas,pci-r9a06g032 # RZ/N1D
35 - const: renesas,pci-rzn1 # RZ/N1
36
37 reg:
38 items:
39 - description: Operational registers for the OHCI/EHCI controllers.
40 - description: Bridge configuration and control registers.
41
42 interrupts:
43 maxItems: 1
44
45 clocks:
46 minItems: 1
47 maxItems: 3
48
49 clock-names:
50 minItems: 1
51 maxItems: 3
52
53 resets:
54 maxItems: 1
55
56 power-domains:
57 maxItems: 1
58
59 bus-range:
60 description: |
61 The PCI bus number range; as this is a single bus, the range
62 should be specified as the same value twice.
63
64 dma-ranges:
65 description: |
66 A single range for the inbound memory region. If not supplied,
67 defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
68 the allowed combinations of address and size.
69 maxItems: 1
70
71 patternProperties:
72 '^usb@[0-1],0$':
73 type: object
74
75 description:
76 This a USB controller PCI device
77
78 properties:
79 reg:
80 description:
81 Identify the correct bus, device and function number in the
82 form <bdf 0 0 0 0>.
83
84 items:
85 minItems: 5
86 maxItems: 5
87
88 phys:
89 description:
90 Reference to the USB phy
91 maxItems: 1
92
93 phy-names:
94 maxItems: 1
95
96 required:
97 - reg
98 - phys
99 - phy-names
100
101 unevaluatedProperties: false
102
103 required:
104 - compatible
105 - reg
106 - interrupts
107 - interrupt-map
108 - interrupt-map-mask
109 - clocks
110 - power-domains
111 - bus-range
112 - "#address-cells"
113 - "#size-cells"
114 - "#interrupt-cells"
115
116 allOf:
117 - $ref: /schemas/pci/pci-host-bridge.yaml#
118
119 - if:
120 properties:
121 compatible:
122 contains:
123 enum:
124 - renesas,pci-rzn1
125 then:
126 properties:
127 clocks:
128 items:
129 - description: Internal bus clock (AHB) for HOST
130 - description: Internal bus clock (AHB) Power Management
131 - description: PCI clock for USB subsystem
132 clock-names:
133 items:
134 - const: hclkh
135 - const: hclkpm
136 - const: pciclk
137 required:
138 - clock-names
139 else:
140 properties:
141 clocks:
142 items:
143 - description: Device clock
144 clock-names:
145 items:
146 - const: pclk
147 required:
148 - resets
149
150 unevaluatedProperties: false
151
152 examples:
153 - |
154 #include <dt-bindings/interrupt-controller/arm-gic.h>
155 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
156 #include <dt-bindings/power/r8a7790-sysc.h>
157
158 pci@ee090000 {
159 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
160 device_type = "pci";
161 reg = <0xee090000 0xc00>,
162 <0xee080000 0x1100>;
163 clocks = <&cpg CPG_MOD 703>;
164 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
165 resets = <&cpg 703>;
166 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
167
168 bus-range = <0 0>;
169 #address-cells = <3>;
170 #size-cells = <2>;
171 #interrupt-cells = <1>;
172 ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
173 dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
174 interrupt-map-mask = <0xf800 0 0 0x7>;
175 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
176 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
177 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
178
179 usb@1,0 {
180 reg = <0x800 0 0 0 0>;
181 phys = <&usb0 0>;
182 phy-names = "usb";
183 };
184
185 usb@2,0 {
186 reg = <0x1000 0 0 0 0>;
187 phys = <&usb0 0>;
188 phy-names = "usb";
189 };
190 };
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