1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip AXI PCIe Endpoint
8
9 maintainers:
10 - Shawn Lin <shawn.lin@rock-chips.com>
11
12 allOf:
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
15
16 properties:
17 compatible:
18 const: rockchip,rk3399-pcie-ep
19
20 reg: true
21
22 reg-names:
23 items:
24 - const: apb-base
25 - const: mem-base
26
27 rockchip,max-outbound-regions:
28 description: Maximum number of outbound regions
29 $ref: /schemas/types.yaml#/definitions/uint32
30 maximum: 32
31 default: 32
32
33 required:
34 - rockchip,max-outbound-regions
35
36 unevaluatedProperties: false
37
38 examples:
39 - |
40 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/clock/rk3399-cru.h>
43
44 bus {
45 #address-cells = <2>;
46 #size-cells = <2>;
47
48 pcie-ep@f8000000 {
49 compatible = "rockchip,rk3399-pcie-ep";
50 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
51 reg-names = "apb-base", "mem-base";
52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
54 clock-names = "aclk", "aclk-perf",
55 "hclk", "pm";
56 max-functions = /bits/ 8 <8>;
57 num-lanes = <4>;
58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
61 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
62 "pm", "pclk", "aclk";
63 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
65 rockchip,max-outbound-regions = <16>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pcie_clkreqnb_cpm>;
68 };
69 };
70 ...
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