1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Airoha EN7581 PCI-Express PHY
8
9 maintainers:
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11
12 description:
13 The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
14
15 properties:
16 compatible:
17 const: airoha,en7581-pcie-phy
18
19 reg:
20 items:
21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
23 - description: PCIE lane1 base address
24 - description: PCIE lane0 detection time base address
25 - description: PCIE lane1 detection time base address
26 - description: PCIE Rx AEQ base address
27
28 reg-names:
29 items:
30 - const: csr-2l
31 - const: pma0
32 - const: pma1
33 - const: p0-xr-dtime
34 - const: p1-xr-dtime
35 - const: rx-aeq
36
37 "#phy-cells":
38 const: 0
39
40 required:
41 - compatible
42 - reg
43 - reg-names
44 - "#phy-cells"
45
46 additionalProperties: false
47
48 examples:
49 - |
50 #include <dt-bindings/phy/phy.h>
51
52 soc {
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 phy@11e80000 {
57 compatible = "airoha,en7581-pcie-phy";
58 #phy-cells = <0>;
59 reg = <0x0 0x1fa5a000 0x0 0xfff>,
60 <0x0 0x1fa5b000 0x0 0xfff>,
61 <0x0 0x1fa5c000 0x0 0xfff>,
62 <0x0 0x1fc10044 0x0 0x4>,
63 <0x0 0x1fc30044 0x0 0x4>,
64 <0x0 0x1fc15030 0x0 0x104>;
65 reg-names = "csr-2l", "pma0", "pma1",
66 "p0-xr-dtime", "p1-xr-dtime",
67 "rx-aeq";
68 };
69 };
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