1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Intel ComboPhy Subsystem
8
9 maintainers:
10 - Dilip Kota <eswara.kota@linux.intel.com>
11
12 description: |
13 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
14 controllers. A single Combophy provides two PHY instances.
15
16 properties:
17 $nodename:
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
19
20 compatible:
21 items:
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
24
25 clocks:
26 maxItems: 1
27
28 reg:
29 items:
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
32
33 reg-names:
34 items:
35 - const: core
36 - const: app
37
38 resets:
39 maxItems: 4
40
41 reset-names:
42 items:
43 - const: phy
44 - const: core
45 - const: iphy0
46 - const: iphy1
47
48 intel,syscfg:
49 $ref: /schemas/types.yaml#/definitions/phandle-array
50 items:
51 - items:
52 - description: phandle to Chip configuration registers
53 - description: ComboPhy instance id
54 description: Chip configuration registers handle and ComboPhy instance id
55
56 intel,hsio:
57 $ref: /schemas/types.yaml#/definitions/phandle-array
58 items:
59 - items:
60 - description: phandle to HSIO registers
61 - description: ComboPhy instance id
62 description: HSIO registers handle and ComboPhy instance id on NOC
63
64 intel,aggregation:
65 type: boolean
66 description: |
67 Specify the flag to configure ComboPHY in dual lane mode.
68
69 intel,phy-mode:
70 $ref: /schemas/types.yaml#/definitions/uint32
71 description: |
72 Mode of the two phys in ComboPhy.
73 See dt-bindings/phy/phy.h for values.
74
75 "#phy-cells":
76 const: 1
77
78 required:
79 - compatible
80 - clocks
81 - reg
82 - reg-names
83 - intel,syscfg
84 - intel,hsio
85 - intel,phy-mode
86 - "#phy-cells"
87
88 additionalProperties: false
89
90 examples:
91 - |
92 #include <dt-bindings/phy/phy.h>
93 combophy@d0a00000 {
94 compatible = "intel,combophy-lgm", "intel,combo-phy";
95 clocks = <&cgu0 1>;
96 #phy-cells = <1>;
97 reg = <0xd0a00000 0x40000>,
98 <0xd0a40000 0x1000>;
99 reg-names = "core", "app";
100 resets = <&rcu0 0x50 6>,
101 <&rcu0 0x50 17>,
102 <&rcu0 0x50 23>,
103 <&rcu0 0x50 24>;
104 reset-names = "phy", "core", "iphy0", "iphy1";
105 intel,syscfg = <&sysconf 0>;
106 intel,hsio = <&hsiol 0>;
107 intel,phy-mode = <PHY_TYPE_PCIE>;
108 intel,aggregation;
109 };
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