1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek MT7988 XFI T-PHY
8
9 maintainers:
10 - Daniel Golle <daniel@makrotopia.org>
11
12 description:
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
15 MediaTek's 10G-capabale MT7988 SoC.
16 In MediaTek's SDK sources, this unit is referred to as "pextp".
17
18 properties:
19 compatible:
20 const: mediatek,mt7988-xfi-tphy
21
22 reg:
23 maxItems: 1
24
25 clocks:
26 items:
27 - description: XFI PHY clock
28 - description: XFI register clock
29
30 clock-names:
31 items:
32 - const: xfipll
33 - const: topxtal
34
35 resets:
36 items:
37 - description: Reset controller corresponding to the phy instance.
38
39 mediatek,usxgmii-performance-errata:
40 $ref: /schemas/types.yaml#/definitions/flag
41 description:
42 One instance of the T-PHY on MT7988 suffers from a performance
43 problem in 10GBase-R mode which needs a work-around in the driver.
44 This flag enables a work-around adjusting an analog phy setting and
45 is required for XFI Port0 of the MT7988 SoC to be in compliance with
46 the SFP specification.
47
48 "#phy-cells":
49 const: 0
50
51 required:
52 - compatible
53 - reg
54 - clocks
55 - clock-names
56 - resets
57 - "#phy-cells"
58
59 additionalProperties: false
60
61 examples:
62 - |
63 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
64 soc {
65 #address-cells = <2>;
66 #size-cells = <2>;
67
68 phy@11f20000 {
69 compatible = "mediatek,mt7988-xfi-tphy";
70 reg = <0 0x11f20000 0 0x10000>;
71 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
72 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
73 clock-names = "xfipll", "topxtal";
74 resets = <&watchdog 14>;
75 mediatek,usxgmii-performance-errata;
76 #phy-cells = <0>;
77 };
78 };
79
80 ...
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