1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Cadence Sierra PHY
8
9 description:
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
11 multiprotocol combinations including protocols such as PCIe, USB etc.
12
13 maintainers:
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
16
17 properties:
18 compatible:
19 enum:
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
22
23 '#address-cells':
24 const: 1
25
26 '#size-cells':
27 const: 0
28
29 '#clock-cells':
30 const: 1
31
32 resets:
33 minItems: 1
34 items:
35 - description: Sierra PHY reset.
36 - description: Sierra APB reset. This is optional.
37
38 reset-names:
39 minItems: 1
40 items:
41 - const: sierra_reset
42 - const: sierra_apb
43
44 reg:
45 maxItems: 1
46 description:
47 Offset of the Sierra PHY configuration registers.
48
49 reg-names:
50 const: serdes
51
52 clocks:
53 minItems: 2
54 maxItems: 4
55
56 clock-names:
57 minItems: 2
58 items:
59 - const: cmn_refclk_dig_div
60 - const: cmn_refclk1_dig_div
61 - const: pll0_refclk
62 - const: pll1_refclk
63
64 cdns,autoconf:
65 type: boolean
66 description:
67 A boolean property whose presence indicates that the PHY registers will be
68 configured by hardware. If not present, all sub-node optional properties
69 must be provided.
70
71 patternProperties:
72 '^phy@[0-9a-f]$':
73 type: object
74 description:
75 Each group of PHY lanes with a single master lane should be represented as
76 a sub-node. Note that the actual configuration of each lane is determined
77 by hardware strapping, and must match the configuration specified here.
78 properties:
79 reg:
80 description:
81 The master lane number. This is the lowest numbered lane in the lane group.
82 minimum: 0
83 maximum: 15
84
85 resets:
86 minItems: 1
87 maxItems: 4
88 description:
89 Contains list of resets, one per lane, to get all the link lanes out of reset.
90
91 "#phy-cells":
92 const: 0
93
94 cdns,phy-type:
95 description:
96 Specifies the type of PHY for which the group of PHY lanes is used.
97 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
98 $ref: /schemas/types.yaml#/definitions/uint32
99 enum: [2, 4]
100
101 cdns,num-lanes:
102 description:
103 Number of lanes in this group. The group is made up of consecutive lanes.
104 $ref: /schemas/types.yaml#/definitions/uint32
105 minimum: 1
106 maximum: 16
107
108 cdns,ssc-mode:
109 description:
110 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
111 EXTERNAL_SSC or INTERNAL_SSC.
112 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
113 $ref: /schemas/types.yaml#/definitions/uint32
114 enum: [0, 1, 2]
115 default: 1
116
117 required:
118 - reg
119 - resets
120 - "#phy-cells"
121
122 additionalProperties: false
123
124 required:
125 - compatible
126 - "#address-cells"
127 - "#size-cells"
128 - reg
129 - resets
130 - reset-names
131
132 additionalProperties: false
133
134 examples:
135 - |
136 #include <dt-bindings/phy/phy.h>
137
138 bus {
139 #address-cells = <2>;
140 #size-cells = <2>;
141
142 sierra-phy@fd240000 {
143 compatible = "cdns,sierra-phy-t0";
144 reg = <0x0 0xfd240000 0x0 0x40000>;
145 resets = <&phyrst 0>, <&phyrst 1>;
146 reset-names = "sierra_reset", "sierra_apb";
147 clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
148 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
149 #address-cells = <1>;
150 #size-cells = <0>;
151 pcie0_phy0: phy@0 {
152 reg = <0>;
153 resets = <&phyrst 2>;
154 cdns,num-lanes = <2>;
155 #phy-cells = <0>;
156 cdns,phy-type = <PHY_TYPE_PCIE>;
157 };
158 pcie0_phy1: phy@2 {
159 reg = <2>;
160 resets = <&phyrst 4>;
161 cdns,num-lanes = <1>;
162 #phy-cells = <0>;
163 cdns,phy-type = <PHY_TYPE_PCIE>;
164 };
165 };
166 };
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