1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
8
9 maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12 description:
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16 properties:
17 compatible:
18 enum:
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,ipq9574-qmp-gen3x1-pcie-phy
23 - qcom,ipq9574-qmp-gen3x2-pcie-phy
24
25 reg:
26 items:
27 - description: serdes
28
29 clocks:
30 maxItems: 3
31
32 clock-names:
33 items:
34 - const: aux
35 - const: cfg_ahb
36 - const: pipe
37
38 resets:
39 maxItems: 2
40
41 reset-names:
42 items:
43 - const: phy
44 - const: common
45
46 "#clock-cells":
47 const: 0
48
49 clock-output-names:
50 maxItems: 1
51
52 "#phy-cells":
53 const: 0
54
55 required:
56 - compatible
57 - reg
58 - clocks
59 - clock-names
60 - resets
61 - reset-names
62 - "#clock-cells"
63 - clock-output-names
64 - "#phy-cells"
65
66 additionalProperties: false
67
68 examples:
69 - |
70 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
71 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
72
73 phy@84000 {
74 compatible = "qcom,ipq6018-qmp-pcie-phy";
75 reg = <0x00084000 0x1000>;
76
77 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
78 <&gcc GCC_PCIE0_AHB_CLK>,
79 <&gcc GCC_PCIE0_PIPE_CLK>;
80 clock-names = "aux",
81 "cfg_ahb",
82 "pipe";
83
84 clock-output-names = "gcc_pcie0_pipe_clk_src";
85 #clock-cells = <0>;
86
87 #phy-cells = <0>;
88
89 resets = <&gcc GCC_PCIE0_PHY_BCR>,
90 <&gcc GCC_PCIE0PHY_PHY_BCR>;
91 reset-names = "phy",
92 "common";
93 };
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