1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm PCIe2 PHY controller
8
9 maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12 description:
13 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
14 platforms.
15
16 properties:
17 compatible:
18 items:
19 - const: qcom,qcs404-pcie2-phy
20 - const: qcom,pcie2-phy
21
22 reg:
23 items:
24 - description: PHY register set
25
26 clocks:
27 items:
28 - description: a clock-specifier pair for the "pipe" clock
29
30 clock-output-names:
31 maxItems: 1
32
33 "#clock-cells":
34 const: 0
35
36 "#phy-cells":
37 const: 0
38
39 vdda-vp-supply:
40 description: low voltage regulator
41
42 vdda-vph-supply:
43 description: high voltage regulator
44
45 resets:
46 maxItems: 2
47
48 reset-names:
49 items:
50 - const: phy
51 - const: pipe
52
53 required:
54 - compatible
55 - reg
56 - clocks
57 - clock-output-names
58 - "#clock-cells"
59 - "#phy-cells"
60 - vdda-vp-supply
61 - vdda-vph-supply
62 - resets
63 - reset-names
64
65 additionalProperties: false
66
67 examples:
68 - |
69 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
70 phy@7786000 {
71 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
72 reg = <0x07786000 0xb8>;
73
74 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
75 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
76 <&gcc GCC_PCIE_0_PIPE_ARES>;
77 reset-names = "phy", "pipe";
78
79 vdda-vp-supply = <&vreg_l3_1p05>;
80 vdda-vph-supply = <&vreg_l5_1p8>;
81
82 clock-output-names = "pcie_0_pipe_clk";
83 #clock-cells = <0>;
84 #phy-cells = <0>;
85 };
86 ...
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