1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9 maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12 description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16 properties:
17 compatible:
18 enum:
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
26 - qcom,sdm845-qmp-pcie-phy
27 - qcom,sdx55-qmp-pcie-phy
28 - qcom,sdx65-qmp-gen4x2-pcie-phy
29 - qcom,sm8150-qmp-gen3x1-pcie-phy
30 - qcom,sm8150-qmp-gen3x2-pcie-phy
31 - qcom,sm8250-qmp-gen3x1-pcie-phy
32 - qcom,sm8250-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-modem-pcie-phy
34 - qcom,sm8350-qmp-gen3x1-pcie-phy
35 - qcom,sm8450-qmp-gen3x1-pcie-phy
36 - qcom,sm8450-qmp-gen4x2-pcie-phy
37 - qcom,sm8550-qmp-gen3x2-pcie-phy
38 - qcom,sm8550-qmp-gen4x2-pcie-phy
39 - qcom,sm8650-qmp-gen3x2-pcie-phy
40 - qcom,sm8650-qmp-gen4x2-pcie-phy
41 - qcom,x1e80100-qmp-gen3x2-pcie-phy
42 - qcom,x1e80100-qmp-gen4x2-pcie-phy
43 - qcom,x1e80100-qmp-gen4x4-pcie-phy
44
45 reg:
46 minItems: 1
47 maxItems: 2
48
49 clocks:
50 minItems: 5
51 maxItems: 7
52
53 clock-names:
54 minItems: 5
55 items:
56 - const: aux
57 - const: cfg_ahb
58 - const: ref
59 - enum: [rchng, refgen]
60 - const: pipe
61 - const: pipediv2
62 - const: phy_aux
63
64 power-domains:
65 maxItems: 1
66
67 resets:
68 minItems: 1
69 maxItems: 2
70
71 reset-names:
72 minItems: 1
73 items:
74 - const: phy
75 - const: phy_nocsr
76
77 vdda-phy-supply: true
78
79 vdda-pll-supply: true
80
81 vdda-qref-supply: true
82
83 qcom,4ln-config-sel:
84 description: PCIe 4-lane configuration
85 $ref: /schemas/types.yaml#/definitions/phandle-array
86 items:
87 - items:
88 - description: phandle of TCSR syscon
89 - description: offset of PCIe 4-lane configuration register
90 - description: offset of configuration bit for this PHY
91
92 "#clock-cells": true
93
94 clock-output-names:
95 maxItems: 1
96
97 "#phy-cells":
98 const: 0
99
100 required:
101 - compatible
102 - reg
103 - clocks
104 - clock-names
105 - resets
106 - reset-names
107 - vdda-phy-supply
108 - vdda-pll-supply
109 - "#clock-cells"
110 - clock-output-names
111 - "#phy-cells"
112
113 additionalProperties: false
114
115 allOf:
116 - if:
117 properties:
118 compatible:
119 contains:
120 enum:
121 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
122 - qcom,x1e80100-qmp-gen4x4-pcie-phy
123 then:
124 properties:
125 reg:
126 items:
127 - description: port a
128 - description: port b
129 required:
130 - qcom,4ln-config-sel
131 else:
132 properties:
133 reg:
134 maxItems: 1
135
136 - if:
137 properties:
138 compatible:
139 contains:
140 enum:
141 - qcom,sc8180x-qmp-pcie-phy
142 - qcom,sdm845-qhp-pcie-phy
143 - qcom,sdm845-qmp-pcie-phy
144 - qcom,sdx55-qmp-pcie-phy
145 - qcom,sm8150-qmp-gen3x1-pcie-phy
146 - qcom,sm8150-qmp-gen3x2-pcie-phy
147 - qcom,sm8250-qmp-gen3x1-pcie-phy
148 - qcom,sm8250-qmp-gen3x2-pcie-phy
149 - qcom,sm8250-qmp-modem-pcie-phy
150 - qcom,sm8350-qmp-gen3x1-pcie-phy
151 - qcom,sm8450-qmp-gen3x1-pcie-phy
152 - qcom,sm8450-qmp-gen3x2-pcie-phy
153 - qcom,sm8550-qmp-gen3x2-pcie-phy
154 - qcom,sm8550-qmp-gen4x2-pcie-phy
155 - qcom,sm8650-qmp-gen3x2-pcie-phy
156 - qcom,sm8650-qmp-gen4x2-pcie-phy
157 then:
158 properties:
159 clocks:
160 maxItems: 5
161 clock-names:
162 maxItems: 5
163
164 - if:
165 properties:
166 compatible:
167 contains:
168 enum:
169 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
170 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
171 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
172 - qcom,x1e80100-qmp-gen3x2-pcie-phy
173 - qcom,x1e80100-qmp-gen4x2-pcie-phy
174 - qcom,x1e80100-qmp-gen4x4-pcie-phy
175 then:
176 properties:
177 clocks:
178 minItems: 6
179 clock-names:
180 minItems: 6
181
182 - if:
183 properties:
184 compatible:
185 contains:
186 enum:
187 - qcom,sa8775p-qmp-gen4x2-pcie-phy
188 - qcom,sa8775p-qmp-gen4x4-pcie-phy
189 then:
190 properties:
191 clocks:
192 minItems: 7
193 clock-names:
194 minItems: 7
195
196 - if:
197 properties:
198 compatible:
199 contains:
200 enum:
201 - qcom,sm8550-qmp-gen4x2-pcie-phy
202 - qcom,sm8650-qmp-gen4x2-pcie-phy
203 - qcom,x1e80100-qmp-gen4x2-pcie-phy
204 - qcom,x1e80100-qmp-gen4x4-pcie-phy
205 then:
206 properties:
207 resets:
208 minItems: 2
209 reset-names:
210 minItems: 2
211 else:
212 properties:
213 resets:
214 maxItems: 1
215 reset-names:
216 maxItems: 1
217
218 - if:
219 properties:
220 compatible:
221 contains:
222 enum:
223 - qcom,sm8450-qmp-gen4x2-pcie-phy
224 - qcom,sm8550-qmp-gen4x2-pcie-phy
225 - qcom,sm8650-qmp-gen4x2-pcie-phy
226 then:
227 properties:
228 "#clock-cells":
229 const: 1
230 else:
231 properties:
232 "#clock-cells":
233 const: 0
234
235 examples:
236 - |
237 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
238
239 pcie2b_phy: phy@1c18000 {
240 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
241 reg = <0x01c18000 0x2000>;
242
243 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
244 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
245 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
246 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
247 <&gcc GCC_PCIE_2B_PIPE_CLK>,
248 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
249 clock-names = "aux", "cfg_ahb", "ref", "rchng",
250 "pipe", "pipediv2";
251
252 power-domains = <&gcc PCIE_2B_GDSC>;
253
254 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
255 reset-names = "phy";
256
257 vdda-phy-supply = <&vreg_l6d>;
258 vdda-pll-supply = <&vreg_l4d>;
259
260 #clock-cells = <0>;
261 clock-output-names = "pcie_2b_pipe_clk";
262
263 #phy-cells = <0>;
264 };
265
266 pcie2a_phy: phy@1c24000 {
267 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
268 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
269
270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
274 <&gcc GCC_PCIE_2A_PIPE_CLK>,
275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
276 clock-names = "aux", "cfg_ahb", "ref", "rchng",
277 "pipe", "pipediv2";
278
279 power-domains = <&gcc PCIE_2A_GDSC>;
280
281 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
282 reset-names = "phy";
283
284 vdda-phy-supply = <&vreg_l6d>;
285 vdda-pll-supply = <&vreg_l4d>;
286
287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
288
289 #clock-cells = <0>;
290 clock-output-names = "pcie_2a_pipe_clk";
291
292 #phy-cells = <0>;
293 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.