1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9 maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12 description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16 properties:
17 compatible:
18 enum:
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
22 - qcom,sc8280xp-qmp-usb43dp-phy
23 - qcom,sdm845-qmp-usb3-dp-phy
24 - qcom,sm6350-qmp-usb3-dp-phy
25 - qcom,sm8150-qmp-usb3-dp-phy
26 - qcom,sm8250-qmp-usb3-dp-phy
27 - qcom,sm8350-qmp-usb3-dp-phy
28 - qcom,sm8450-qmp-usb3-dp-phy
29 - qcom,sm8550-qmp-usb3-dp-phy
30 - qcom,sm8650-qmp-usb3-dp-phy
31 - qcom,x1e80100-qmp-usb3-dp-phy
32
33 reg:
34 maxItems: 1
35
36 clocks:
37 minItems: 4
38 maxItems: 5
39
40 clock-names:
41 minItems: 4
42 items:
43 - const: aux
44 - const: ref
45 - const: com_aux
46 - const: usb3_pipe
47 - const: cfg_ahb
48
49 power-domains:
50 maxItems: 1
51
52 resets:
53 maxItems: 2
54
55 reset-names:
56 items:
57 - const: phy
58 - const: common
59
60 vdda-phy-supply: true
61
62 vdda-pll-supply: true
63
64 "#clock-cells":
65 const: 1
66 description:
67 See include/dt-bindings/phy/phy-qcom-qmp.h
68
69 "#phy-cells":
70 const: 1
71 description:
72 See include/dt-bindings/phy/phy-qcom-qmp.h
73
74 orientation-switch:
75 description:
76 Flag the PHY as possible handler of USB Type-C orientation switching
77 type: boolean
78
79 ports:
80 $ref: /schemas/graph.yaml#/properties/ports
81 properties:
82 port@0:
83 $ref: /schemas/graph.yaml#/properties/port
84 description: Output endpoint of the PHY
85
86 port@1:
87 $ref: /schemas/graph.yaml#/properties/port
88 description: Incoming endpoint from the USB controller
89
90 port@2:
91 $ref: /schemas/graph.yaml#/properties/port
92 description: Incoming endpoint from the DisplayPort controller
93
94 required:
95 - compatible
96 - reg
97 - clocks
98 - clock-names
99 - resets
100 - reset-names
101 - vdda-phy-supply
102 - vdda-pll-supply
103 - "#clock-cells"
104 - "#phy-cells"
105
106 allOf:
107 - if:
108 properties:
109 compatible:
110 enum:
111 - qcom,sc7180-qmp-usb3-dp-phy
112 - qcom,sdm845-qmp-usb3-dp-phy
113 then:
114 properties:
115 clocks:
116 maxItems: 5
117 clock-names:
118 maxItems: 5
119 else:
120 properties:
121 clocks:
122 maxItems: 4
123 clock-names:
124 maxItems: 4
125
126 - if:
127 properties:
128 compatible:
129 enum:
130 - qcom,sc8280xp-qmp-usb43dp-phy
131 - qcom,sm6350-qmp-usb3-dp-phy
132 - qcom,sm8550-qmp-usb3-dp-phy
133 - qcom,sm8650-qmp-usb3-dp-phy
134 - qcom,x1e80100-qmp-usb3-dp-phy
135 then:
136 required:
137 - power-domains
138 else:
139 properties:
140 power-domains: false
141
142 additionalProperties: false
143
144 examples:
145 - |
146 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
147
148 phy@88eb000 {
149 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
150 reg = <0x088eb000 0x4000>;
151
152 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
153 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
154 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
155 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
156 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
157
158 power-domains = <&gcc USB30_PRIM_GDSC>;
159
160 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
161 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
162 reset-names = "phy", "common";
163
164 vdda-phy-supply = <&vreg_l9d>;
165 vdda-pll-supply = <&vreg_l4d>;
166
167 orientation-switch;
168
169 #clock-cells = <1>;
170 #phy-cells = <1>;
171
172 ports {
173 #address-cells = <1>;
174 #size-cells = <0>;
175
176 port@0 {
177 reg = <0>;
178
179 endpoint {
180 remote-endpoint = <&typec_connector_ss>;
181 };
182 };
183
184 port@1 {
185 reg = <1>;
186
187 endpoint {
188 remote-endpoint = <&dwc3_ss_out>;
189 };
190 };
191
192 port@2 {
193 reg = <2>;
194
195 endpoint {
196 remote-endpoint = <&mdss_dp_out>;
197 };
198 };
199 };
200 };
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