1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip USB2.0 phy with inno IP block
8
9 maintainers:
10 - Heiko Stuebner <heiko@sntech.de>
11
12 properties:
13 compatible:
14 enum:
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
20 - rockchip,rk3366-usb2phy
21 - rockchip,rk3399-usb2phy
22 - rockchip,rk3568-usb2phy
23 - rockchip,rk3588-usb2phy
24 - rockchip,rv1108-usb2phy
25
26 reg:
27 maxItems: 1
28
29 clock-output-names:
30 description:
31 The usb 480m output clock name.
32
33 "#clock-cells":
34 const: 0
35
36 clocks:
37 maxItems: 1
38
39 clock-names:
40 const: phyclk
41
42 assigned-clocks:
43 description:
44 Phandle of the usb 480m clock.
45
46 assigned-clock-parents:
47 description:
48 Parent of the usb 480m clock.
49 Select between usb-phy output 480m and xin24m.
50 Refer to clk/clock-bindings.txt for generic clock consumer properties.
51
52 extcon:
53 description:
54 Phandle to the extcon device providing the cable state for the otg phy.
55
56 interrupts:
57 description: Muxed interrupt for both ports
58 maxItems: 1
59
60 resets:
61 maxItems: 2
62
63 reset-names:
64 items:
65 - const: phy
66 - const: apb
67
68 rockchip,usbgrf:
69 $ref: /schemas/types.yaml#/definitions/phandle
70 description:
71 Phandle to the syscon managing the 'usb general register files'.
72 When set the driver will request its phandle as one companion-grf
73 for some special SoCs (e.g rv1108).
74
75 host-port:
76 type: object
77 additionalProperties: false
78
79 properties:
80 "#phy-cells":
81 const: 0
82
83 interrupts:
84 description: host linestate interrupt
85 maxItems: 1
86
87 interrupt-names:
88 const: linestate
89
90 phy-supply:
91 description:
92 Phandle to a regulator that provides power to VBUS.
93 See ./phy-bindings.txt for details.
94
95 required:
96 - "#phy-cells"
97
98 otg-port:
99 type: object
100 additionalProperties: false
101
102 properties:
103 "#phy-cells":
104 const: 0
105
106 interrupts:
107 minItems: 1
108 maxItems: 3
109
110 interrupt-names:
111 oneOf:
112 - const: linestate
113 - const: otg-mux
114 - items:
115 - const: otg-bvalid
116 - const: otg-id
117 - const: linestate
118
119 phy-supply:
120 description:
121 Phandle to a regulator that provides power to VBUS.
122 See ./phy-bindings.txt for details.
123
124 required:
125 - "#phy-cells"
126
127 required:
128 - compatible
129 - reg
130 - clock-output-names
131 - "#clock-cells"
132
133 anyOf:
134 - required:
135 - otg-port
136 - required:
137 - host-port
138
139 allOf:
140 - if:
141 properties:
142 compatible:
143 contains:
144 enum:
145 - rockchip,rk3568-usb2phy
146 - rockchip,rk3588-usb2phy
147
148 then:
149 properties:
150 host-port:
151 properties:
152 interrupts: false
153
154 otg-port:
155 properties:
156 interrupts: false
157
158 required:
159 - interrupts
160
161 else:
162 properties:
163 interrupts: false
164
165 host-port:
166 required:
167 - interrupts
168 - interrupt-names
169
170 otg-port:
171 required:
172 - interrupts
173 - interrupt-names
174
175 additionalProperties: false
176
177 examples:
178 - |
179 #include <dt-bindings/clock/rk3399-cru.h>
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/interrupt-controller/irq.h>
182 u2phy0: usb2phy@e450 {
183 compatible = "rockchip,rk3399-usb2phy";
184 reg = <0xe450 0x10>;
185 clocks = <&cru SCLK_USB2PHY0_REF>;
186 clock-names = "phyclk";
187 clock-output-names = "clk_usbphy0_480m";
188 #clock-cells = <0>;
189
190 u2phy0_host: host-port {
191 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
192 interrupt-names = "linestate";
193 #phy-cells = <0>;
194 };
195
196 u2phy0_otg: otg-port {
197 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
198 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
199 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
200 interrupt-names = "otg-bvalid", "otg-id", "linestate";
201 #phy-cells = <0>;
202 };
203 };
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