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Linux/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Rockchip SoC MIPI RX0 D-PHY
  8 
  9 maintainers:
 10   - Heiko Stuebner <heiko@sntech.de>
 11 
 12 description: |
 13   The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
 14   connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
 15 
 16 properties:
 17   compatible:
 18     enum:
 19       - rockchip,px30-csi-dphy
 20       - rockchip,rk1808-csi-dphy
 21       - rockchip,rk3326-csi-dphy
 22       - rockchip,rk3368-csi-dphy
 23       - rockchip,rk3568-csi-dphy
 24 
 25   reg:
 26     maxItems: 1
 27 
 28   clocks:
 29     maxItems: 1
 30 
 31   clock-names:
 32     const: pclk
 33 
 34   '#phy-cells':
 35     const: 0
 36 
 37   power-domains:
 38     description: Video in/out power domain.
 39     maxItems: 1
 40 
 41   resets:
 42     items:
 43       - description: exclusive PHY reset line
 44 
 45   reset-names:
 46     items:
 47       - const: apb
 48 
 49   rockchip,grf:
 50     $ref: /schemas/types.yaml#/definitions/phandle
 51     description:
 52       Some additional phy settings are access through GRF regs.
 53 
 54 required:
 55   - compatible
 56   - reg
 57   - clocks
 58   - clock-names
 59   - '#phy-cells'
 60   - power-domains
 61   - resets
 62   - reset-names
 63   - rockchip,grf
 64 
 65 additionalProperties: false
 66 
 67 examples:
 68   - |
 69 
 70     csi_dphy: phy@ff2f0000 {
 71         compatible = "rockchip,px30-csi-dphy";
 72         reg = <0xff2f0000 0x4000>;
 73         clocks = <&cru 1>;
 74         clock-names = "pclk";
 75         #phy-cells = <0>;
 76         power-domains = <&power 1>;
 77         resets = <&cru 1>;
 78         reset-names = "apb";
 79         rockchip,grf = <&grf>;
 80     };

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