1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Socionext UniPhier PCIe PHY
8
9 description: |
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
12
13 maintainers:
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15
16 properties:
17 compatible:
18 enum:
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
22 - socionext,uniphier-nx1-pcie-phy
23
24 reg:
25 maxItems: 1
26
27 "#phy-cells":
28 const: 0
29
30 clocks:
31 minItems: 1
32 maxItems: 2
33
34 clock-names:
35 minItems: 1
36 maxItems: 2
37
38 resets:
39 minItems: 1
40 maxItems: 2
41
42 reset-names:
43 minItems: 1
44 maxItems: 2
45
46 socionext,syscon:
47 $ref: /schemas/types.yaml#/definitions/phandle
48 description: A phandle to system control to set configurations for phy
49
50 allOf:
51 - if:
52 properties:
53 compatible:
54 contains:
55 const: socionext,uniphier-pro5-pcie-phy
56 then:
57 properties:
58 clocks:
59 minItems: 2
60 maxItems: 2
61 clock-names:
62 items:
63 - const: gio
64 - const: link
65 resets:
66 minItems: 2
67 maxItems: 2
68 reset-names:
69 items:
70 - const: gio
71 - const: link
72 else:
73 properties:
74 clocks:
75 maxItems: 1
76 clock-names:
77 const: link
78 resets:
79 maxItems: 1
80 reset-names:
81 const: link
82
83 required:
84 - compatible
85 - reg
86 - "#phy-cells"
87 - clocks
88 - clock-names
89 - resets
90 - reset-names
91
92 additionalProperties: false
93
94 examples:
95 - |
96 pcie_phy: phy@66038000 {
97 compatible = "socionext,uniphier-ld20-pcie-phy";
98 reg = <0x66038000 0x4000>;
99 #phy-cells = <0>;
100 clock-names = "link";
101 clocks = <&sys_clk 24>;
102 reset-names = "link";
103 resets = <&sys_rst 24>;
104 socionext,syscon = <&soc_glue>;
105 };
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