1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9 description: |
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
14
15 maintainers:
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18 properties:
19 compatible:
20 enum:
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
23 - socionext,uniphier-ld20-usb3-hsphy
24 - socionext,uniphier-pxs3-usb3-hsphy
25 - socionext,uniphier-nx1-usb3-hsphy
26
27 reg:
28 maxItems: 1
29
30 "#phy-cells":
31 const: 0
32
33 clocks:
34 minItems: 2
35 maxItems: 3
36
37 clock-names:
38 minItems: 2
39 maxItems: 3
40
41 resets:
42 maxItems: 2
43
44 reset-names:
45 maxItems: 2
46
47 vbus-supply:
48 description: A phandle to the regulator for USB VBUS
49
50 nvmem-cells:
51 maxItems: 3
52 description:
53 Phandles to nvmem cell that contains the trimming data.
54 Available only for HS-PHY implemented on LD20 and PXs3, and
55 if unspecified, default value is used.
56
57 nvmem-cell-names:
58 items:
59 - const: rterm
60 - const: sel_t
61 - const: hs_i
62 description:
63 Should be the following names, which correspond to each nvmem-cells.
64 All of the 3 parameters associated with the above names are
65 required for each port, if any one is omitted, the trimming data
66 of the port will not be set at all.
67
68 allOf:
69 - if:
70 properties:
71 compatible:
72 contains:
73 const: socionext,uniphier-pro5-usb3-hsphy
74 then:
75 properties:
76 clocks:
77 minItems: 2
78 maxItems: 2
79 clock-names:
80 items:
81 - const: gio
82 - const: link
83 resets:
84 minItems: 2
85 maxItems: 2
86 reset-names:
87 items:
88 - const: gio
89 - const: link
90 - if:
91 properties:
92 compatible:
93 contains:
94 enum:
95 - socionext,uniphier-pxs2-usb3-hsphy
96 - socionext,uniphier-ld20-usb3-hsphy
97 then:
98 properties:
99 clocks:
100 minItems: 2
101 maxItems: 2
102 clock-names:
103 items:
104 - const: link
105 - const: phy
106 resets:
107 minItems: 2
108 maxItems: 2
109 reset-names:
110 items:
111 - const: link
112 - const: phy
113 - if:
114 properties:
115 compatible:
116 contains:
117 enum:
118 - socionext,uniphier-pxs3-usb3-hsphy
119 - socionext,uniphier-nx1-usb3-hsphy
120 then:
121 properties:
122 clocks:
123 minItems: 2
124 maxItems: 3
125 clock-names:
126 minItems: 2
127 items:
128 - const: link
129 - const: phy
130 - const: phy-ext
131 resets:
132 minItems: 2
133 maxItems: 2
134 reset-names:
135 items:
136 - const: link
137 - const: phy
138
139 required:
140 - compatible
141 - reg
142 - "#phy-cells"
143 - clocks
144 - clock-names
145 - resets
146 - reset-names
147
148 additionalProperties: false
149
150 examples:
151 - |
152 usb_hsphy0: phy@200 {
153 compatible = "socionext,uniphier-ld20-usb3-hsphy";
154 reg = <0x200 0x10>;
155 #phy-cells = <0>;
156 clock-names = "link", "phy";
157 clocks = <&sys_clk 14>, <&sys_clk 16>;
158 reset-names = "link", "phy";
159 resets = <&sys_rst 14>, <&sys_rst 16>;
160 vbus-supply = <&usb_vbus0>;
161 nvmem-cell-names = "rterm", "sel_t", "hs_i";
162 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
163 };
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