1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek MT6779 Pin Controller
8
9 maintainers:
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
12
13 description:
14 The MediaTek pin controller on MT6779 is used to control pin functions, pull
15 up/down resistance and drive strength options.
16
17 properties:
18 compatible:
19 enum:
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
22
23 reg:
24 description: Physical addresses for GPIO base(s) and EINT registers.
25
26 reg-names: true
27
28 gpio-controller: true
29
30 "#gpio-cells":
31 const: 2
32 description:
33 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
34 the amount of cells must be specified as 2. See the below mentioned gpio
35 binding representation for description of particular cells.
36
37 gpio-ranges:
38 minItems: 1
39 maxItems: 5
40 description:
41 GPIO valid number range.
42
43 interrupt-controller: true
44
45 interrupts:
46 maxItems: 1
47 description:
48 Specifies the summary IRQ.
49
50 "#interrupt-cells":
51 const: 2
52
53 required:
54 - compatible
55 - reg
56 - reg-names
57 - gpio-controller
58 - "#gpio-cells"
59
60 allOf:
61 - $ref: pinctrl.yaml#
62 - if:
63 properties:
64 compatible:
65 contains:
66 const: mediatek,mt6779-pinctrl
67 then:
68 properties:
69 reg:
70 minItems: 9
71 maxItems: 9
72
73 reg-names:
74 items:
75 - const: gpio
76 - const: iocfg_rm
77 - const: iocfg_br
78 - const: iocfg_lm
79 - const: iocfg_lb
80 - const: iocfg_rt
81 - const: iocfg_lt
82 - const: iocfg_tl
83 - const: eint
84 - if:
85 properties:
86 compatible:
87 contains:
88 const: mediatek,mt6797-pinctrl
89 then:
90 properties:
91 reg:
92 minItems: 5
93 maxItems: 5
94
95 reg-names:
96 items:
97 - const: gpio
98 - const: iocfgl
99 - const: iocfgb
100 - const: iocfgr
101 - const: iocfgt
102 - if:
103 properties:
104 reg-names:
105 contains:
106 const: eint
107 then:
108 required:
109 - interrupts
110 - interrupt-controller
111 - "#interrupt-cells"
112
113 patternProperties:
114 '-[0-9]*$':
115 type: object
116 additionalProperties: false
117
118 patternProperties:
119 '-pins*$':
120 type: object
121 description:
122 A pinctrl node should contain at least one subnodes representing the
123 pinctrl groups available on the machine. Each subnode will list the
124 pins it needs, and how they should be configured, with regard to muxer
125 configuration, pullups, drive strength, input enable/disable and input
126 schmitt.
127 $ref: /schemas/pinctrl/pincfg-node.yaml
128
129 properties:
130 pinmux:
131 description:
132 Integer array, represents gpio pin number and mux setting.
133 Supported pin number and mux varies for different SoCs, and are
134 defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
135
136 bias-disable: true
137
138 bias-pull-up: true
139
140 bias-pull-down: true
141
142 input-enable: true
143
144 input-disable: true
145
146 output-low: true
147
148 output-high: true
149
150 input-schmitt-enable: true
151
152 input-schmitt-disable: true
153
154 drive-strength:
155 enum: [2, 4, 8, 12, 16]
156
157 slew-rate:
158 enum: [0, 1]
159
160 mediatek,pull-up-adv:
161 description: |
162 Pull up settings for 2 pull resistors, R0 and R1. User can
163 configure those special pins. Valid arguments are described as
164 below:
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
168 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
169 $ref: /schemas/types.yaml#/definitions/uint32
170 enum: [0, 1, 2, 3]
171
172 mediatek,pull-down-adv:
173 description: |
174 Pull down settings for 2 pull resistors, R0 and R1. User can
175 configure those special pins. Valid arguments are described as
176 below:
177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
180 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
181 $ref: /schemas/types.yaml#/definitions/uint32
182 enum: [0, 1, 2, 3]
183
184 required:
185 - pinmux
186
187 additionalProperties: false
188
189 additionalProperties: false
190
191 examples:
192 - |
193 #include <dt-bindings/interrupt-controller/irq.h>
194 #include <dt-bindings/interrupt-controller/arm-gic.h>
195 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
196
197 soc {
198 #address-cells = <2>;
199 #size-cells = <2>;
200
201 pio: pinctrl@10005000 {
202 compatible = "mediatek,mt6779-pinctrl";
203 reg = <0 0x10005000 0 0x1000>,
204 <0 0x11c20000 0 0x1000>,
205 <0 0x11d10000 0 0x1000>,
206 <0 0x11e20000 0 0x1000>,
207 <0 0x11e70000 0 0x1000>,
208 <0 0x11ea0000 0 0x1000>,
209 <0 0x11f20000 0 0x1000>,
210 <0 0x11f30000 0 0x1000>,
211 <0 0x1000b000 0 0x1000>;
212 reg-names = "gpio", "iocfg_rm",
213 "iocfg_br", "iocfg_lm",
214 "iocfg_lb", "iocfg_rt",
215 "iocfg_lt", "iocfg_tl",
216 "eint";
217 gpio-controller;
218 #gpio-cells = <2>;
219 gpio-ranges = <&pio 0 0 210>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
223
224 mmc0_pins_default: mmc0-0 {
225 cmd-dat-pins {
226 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
227 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
228 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
229 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
230 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
231 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
232 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
233 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
234 <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
235 input-enable;
236 mediatek,pull-up-adv = <1>;
237 };
238 clk-pins {
239 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
240 mediatek,pull-down-adv = <2>;
241 };
242 rst-pins {
243 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
244 mediatek,pull-up-adv = <0>;
245 };
246 };
247 };
248
249 mmc0 {
250 pinctrl-0 = <&mmc0_pins_default>;
251 pinctrl-names = "default";
252 };
253 };
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