1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek MT7986 Pin Controller
8
9 maintainers:
10 - Sean Wang <sean.wang@kernel.org>
11
12 description:
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
14
15 properties:
16 compatible:
17 enum:
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
20
21 reg:
22 minItems: 8
23 maxItems: 8
24
25 reg-names:
26 items:
27 - const: gpio
28 - const: iocfg_rt
29 - const: iocfg_rb
30 - const: iocfg_lt
31 - const: iocfg_lb
32 - const: iocfg_tr
33 - const: iocfg_tl
34 - const: eint
35
36 gpio-controller: true
37
38 "#gpio-cells":
39 const: 2
40 description:
41 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42 the amount of cells must be specified as 2. See the below mentioned gpio
43 binding representation for description of particular cells.
44
45 gpio-ranges:
46 minItems: 1
47 maxItems: 5
48 description:
49 GPIO valid number range.
50
51 interrupt-controller: true
52
53 interrupts:
54 maxItems: 1
55
56 "#interrupt-cells":
57 const: 2
58
59 allOf:
60 - $ref: pinctrl.yaml#
61
62 required:
63 - compatible
64 - reg
65 - reg-names
66 - gpio-controller
67 - "#gpio-cells"
68
69 patternProperties:
70 '-pins$':
71 type: object
72 additionalProperties: false
73
74 patternProperties:
75 '^.*mux.*$':
76 type: object
77 additionalProperties: false
78 description: |
79 pinmux configuration nodes.
80
81 The following table shows the effective values of "group", "function"
82 properties and chip pinout pins
83
84 groups function pins (in pin#)
85 ---------------------------------------------------------------------
86 "watchdog" "watchdog" 0
87 "wifi_led" "led" 1, 2
88 "i2c" "i2c" 3, 4
89 "uart1_0" "uart" 7, 8, 9, 10
90 "uart1_rx_tx" "uart" 42, 43
91 "uart1_cts_rts" "uart" 44, 45
92 "pcie_clk" "pcie" 9
93 "pcie_wake" "pcie" 10
94 "spi1_0" "spi" 11, 12, 13, 14
95 "pwm1_1" "pwm" 20,
96 "pwm0" "pwm" 21,
97 "pwm1_0" "pwm" 22,
98 "snfi" "flash" 23, 24, 25, 26, 27, 28
99 "spi1_2" "spi" 29, 30, 31, 32
100 "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
101 32
102
103 "spi1_1" "spi" 23, 24, 25, 26
104 "uart1_2_rx_tx" "uart" 29, 30
105 "uart1_2_cts_rts" "uart" 31, 32
106 "uart1_1" "uart" 23, 24, 25, 26
107 "uart2_0_rx_tx" "uart" 29, 30
108 "uart2_0_cts_rts" "uart" 31, 32
109 "spi0" "spi" 33, 34, 35, 36
110 "spi0_wp_hold" "spi" 37, 38
111 "uart1_3_rx_tx" "uart" 35, 36
112 "uart1_3_cts_rts" "uart" 37, 38
113 "uart2_1" "uart" 33, 34, 35, 36
114 "spi1_3" "spi" 33, 34, 35, 36
115 "uart0" "uart" 39, 40
116 "pcie_pereset" "pcie" 41
117 "uart1" "uart" 42, 43, 44, 45
118 "uart2" "uart" 46, 47, 48, 49
119 "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
120 60, 61
121
122 "pcm" "audio" 62, 63, 64, 65
123 "i2s" "audio" 62, 63, 64, 65
124 "switch_int" "eth" 66
125 "mdc_mdio" "eth" 67
126 "wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83
127 "wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100
128 "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
129 84, 85
130
131 $ref: /schemas/pinctrl/pinmux-node.yaml
132 properties:
133 function:
134 description:
135 A string containing the name of the function to mux to the group.
136 There is no "audio", "pcie" functions on mt7986b, you can only use
137 those functions on mt7986a.
138 enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart,
139 watchdog, wifi]
140 groups:
141 description:
142 An array of strings. Each string contains the name of a group.
143 There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and
144 "i2s" groups on mt7986b, you can only use those groups on mt7986a.
145 required:
146 - function
147 - groups
148
149 allOf:
150 - if:
151 properties:
152 function:
153 const: audio
154 then:
155 properties:
156 groups:
157 enum: [pcm, i2s]
158 - if:
159 properties:
160 function:
161 const: emmc
162 then:
163 properties:
164 groups:
165 enum: [emmc_45, emmc_51]
166 - if:
167 properties:
168 function:
169 const: eth
170 then:
171 properties:
172 groups:
173 enum: [switch_int, mdc_mdio]
174 - if:
175 properties:
176 function:
177 const: i2c
178 then:
179 properties:
180 groups:
181 enum: [i2c]
182 - if:
183 properties:
184 function:
185 const: led
186 then:
187 properties:
188 groups:
189 enum: [wifi_led]
190 - if:
191 properties:
192 function:
193 const: flash
194 then:
195 properties:
196 groups:
197 enum: [snfi]
198 - if:
199 properties:
200 function:
201 const: pcie
202 then:
203 properties:
204 groups:
205 items:
206 enum: [pcie_clk, pcie_wake, pcie_pereset]
207 maxItems: 3
208 - if:
209 properties:
210 function:
211 const: pwm
212 then:
213 properties:
214 groups:
215 items:
216 enum: [pwm0, pwm1_0, pwm1_1]
217 maxItems: 2
218 - if:
219 properties:
220 function:
221 const: spi
222 then:
223 properties:
224 groups:
225 items:
226 enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
227 maxItems: 2
228 - if:
229 properties:
230 function:
231 const: uart
232 then:
233 properties:
234 groups:
235 items:
236 enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
237 uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
238 uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
239 uart2_1, uart0, uart1, uart2]
240 maxItems: 2
241 - if:
242 properties:
243 function:
244 const: watchdog
245 then:
246 properties:
247 groups:
248 enum: [watchdog]
249 - if:
250 properties:
251 function:
252 const: wifi
253 then:
254 properties:
255 groups:
256 items:
257 enum: [wf_2g, wf_5g, wf_dbdc]
258 maxItems: 3
259 '^.*conf.*$':
260 type: object
261 additionalProperties: false
262 description:
263 pinconf configuration nodes.
264 $ref: /schemas/pinctrl/pincfg-node.yaml
265
266 properties:
267 pins:
268 description:
269 An array of strings. Each string contains the name of a pin. There
270 is no PIN 41 to PIN 65 above on mt7686b, you can only use those
271 pins on mt7986a.
272 items:
273 enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
274 GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
275 GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13,
276 GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI,
277 SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
278 SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
279 SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
280 UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS,
281 UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS,
282 EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3,
283 EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7,
284 EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX,
285 PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
286 WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
287 WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
288 WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
289 WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
290 WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
291 WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
292 WF1_HB8]
293 maxItems: 101
294
295 bias-disable: true
296
297 bias-pull-up:
298 oneOf:
299 - type: boolean
300 description: normal pull up.
301 - enum: [100, 101, 102, 103]
302 description:
303 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
304 dt-bindings/pinctrl/mt65xx.h.
305
306 bias-pull-down:
307 oneOf:
308 - type: boolean
309 description: normal pull down.
310 - enum: [100, 101, 102, 103]
311 description:
312 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
313 dt-bindings/pinctrl/mt65xx.h.
314
315 input-enable: true
316
317 input-disable: true
318
319 output-enable: true
320
321 output-low: true
322
323 output-high: true
324
325 input-schmitt-enable: true
326
327 input-schmitt-disable: true
328
329 drive-strength:
330 enum: [2, 4, 6, 8, 10, 12, 14, 16]
331
332 mediatek,pull-up-adv:
333 description: |
334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
335 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
336 are described as below:
337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
339 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
340 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
341 $ref: /schemas/types.yaml#/definitions/uint32
342 enum: [0, 1, 2, 3]
343
344 mediatek,pull-down-adv:
345 description: |
346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
347 Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
348 are described as below:
349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
351 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
352 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
353 $ref: /schemas/types.yaml#/definitions/uint32
354 enum: [0, 1, 2, 3]
355
356 required:
357 - pins
358
359 additionalProperties: false
360
361 examples:
362 - |
363 #include <dt-bindings/interrupt-controller/irq.h>
364 #include <dt-bindings/interrupt-controller/arm-gic.h>
365 #include <dt-bindings/pinctrl/mt65xx.h>
366
367 soc {
368 #address-cells = <2>;
369 #size-cells = <2>;
370 pio: pinctrl@1001f000 {
371 compatible = "mediatek,mt7986a-pinctrl";
372 reg = <0 0x1001f000 0 0x1000>,
373 <0 0x11c30000 0 0x1000>,
374 <0 0x11c40000 0 0x1000>,
375 <0 0x11e20000 0 0x1000>,
376 <0 0x11e30000 0 0x1000>,
377 <0 0x11f00000 0 0x1000>,
378 <0 0x11f10000 0 0x1000>,
379 <0 0x1000b000 0 0x1000>;
380 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
381 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
382 gpio-controller;
383 #gpio-cells = <2>;
384 gpio-ranges = <&pio 0 0 100>;
385 interrupt-controller;
386 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-parent = <&gic>;
388 #interrupt-cells = <2>;
389
390 pcie_pins: pcie-pins {
391 mux {
392 function = "pcie";
393 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
394 };
395 };
396
397 pwm_pins: pwm-pins {
398 mux {
399 function = "pwm";
400 groups = "pwm0", "pwm1_0";
401 };
402 };
403
404 spi0_pins: spi0-pins {
405 mux {
406 function = "spi";
407 groups = "spi0", "spi0_wp_hold";
408 };
409 };
410
411 uart1_pins: uart1-pins {
412 mux {
413 function = "uart";
414 groups = "uart1";
415 };
416 };
417
418 uart1_3_pins: uart1-3-pins {
419 mux {
420 function = "uart";
421 groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
422 };
423 };
424
425 uart2_pins: uart2-pins {
426 mux {
427 function = "uart";
428 groups = "uart2";
429 };
430 };
431
432 mmc0_pins_default: mmc0-pins {
433 mux {
434 function = "emmc";
435 groups = "emmc_51";
436 };
437 conf-cmd-dat {
438 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
439 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
440 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
441 input-enable;
442 drive-strength = <4>;
443 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
444 };
445 conf-clk {
446 pins = "EMMC_CK";
447 drive-strength = <6>;
448 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
449 };
450 conf-ds {
451 pins = "EMMC_DSL";
452 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
453 };
454 conf-rst {
455 pins = "EMMC_RSTB";
456 drive-strength = <4>;
457 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
458 };
459 };
460
461 };
462 };
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