1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Nuvoton MA35D1 pin control and GPIO
8
9 maintainers:
10 - Shan-Chun Hung <schung@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
12
13 allOf:
14 - $ref: pinctrl.yaml#
15
16 properties:
17 compatible:
18 enum:
19 - nuvoton,ma35d1-pinctrl
20
21 reg:
22 maxItems: 1
23
24 '#address-cells':
25 const: 1
26
27 '#size-cells':
28 const: 1
29
30 nuvoton,sys:
31 $ref: /schemas/types.yaml#/definitions/phandle
32 description:
33 phandle of the system-management node.
34
35 ranges: true
36
37 patternProperties:
38 "^gpio@[0-9a-f]+$":
39 type: object
40 properties:
41 gpio-controller: true
42
43 '#gpio-cells':
44 const: 2
45
46 reg:
47 maxItems: 1
48
49 clocks:
50 maxItems: 1
51
52 interrupt-controller: true
53
54 '#interrupt-cells':
55 const: 2
56
57 interrupts:
58 description:
59 The interrupt outputs to sysirq.
60 maxItems: 1
61
62 required:
63 - gpio-controller
64 - '#gpio-cells'
65 - reg
66 - clocks
67 - interrupt-controller
68 - '#interrupt-cells'
69 - interrupts
70
71 additionalProperties: false
72
73 "-grp$":
74 type: object
75 description:
76 Pinctrl node's client devices use subnodes for desired pin configuration.
77 Client device subnodes use below standard properties.
78 patternProperties:
79 "-pins$":
80 type: object
81 description:
82 A pinctrl node should contain at least one subnodes representing the
83 pinctrl groups available on the machine. Each subnode will list the
84 pins it needs, and how they should be configured, with regard to muxer
85 configuration, pullups, drive strength, input enable/disable and input
86 schmitt.
87 $ref: /schemas/pinctrl/pincfg-node.yaml
88
89 properties:
90 nuvoton,pins:
91 description:
92 Each entry consists of 4 parameters and represents the mux and config
93 setting for one pin.
94 $ref: /schemas/types.yaml#/definitions/uint32-matrix
95 minItems: 1
96 items:
97 items:
98 - minimum: 0
99 maximum: 13
100 description:
101 Pin bank.
102 - minimum: 0
103 maximum: 15
104 description:
105 Pin bank index.
106 - minimum: 0
107 maximum: 15
108 description:
109 Mux 0 means GPIO and mux 1 to 15 means the specific device function.
110
111 power-source:
112 description: |
113 Valid arguments are described as below:
114 0: power supply of 1.8V
115 1: power supply of 3.3V
116 enum: [0, 1]
117
118 drive-strength-microamp:
119 oneOf:
120 - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
121 description: 1.8V I/O driving strength
122 - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ]
123 description: 3.3V I/O driving strength
124
125 bias-disable: true
126
127 bias-pull-up: true
128
129 bias-pull-down: true
130
131 input-schmitt-disable: true
132
133 additionalProperties: false
134
135 additionalProperties: false
136
137 required:
138 - compatible
139 - reg
140 - nuvoton,sys
141
142 additionalProperties: false
143
144 examples:
145 - |
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/gpio/gpio.h>
148 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
149
150 pinctrl@40040000 {
151 compatible = "nuvoton,ma35d1-pinctrl";
152 reg = <0x40040000 0xc00>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155 nuvoton,sys = <&sys>;
156 ranges = <0x0 0x40040000 0x400>;
157
158 gpio@0 {
159 reg = <0x0 0x40>;
160 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&clk GPA_GATE>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
167
168 uart-grp {
169 uart11-pins {
170 nuvoton,pins = <11 0 2>,
171 <11 1 2>,
172 <11 2 2>,
173 <11 3 2>;
174 power-source = <1>;
175 bias-disable;
176 };
177 };
178 };
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