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Linux/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: NVIDIA Tegra234 Pinmux Controller
  8 
  9 maintainers:
 10   - Thierry Reding <thierry.reding@gmail.com>
 11   - Jon Hunter <jonathanh@nvidia.com>
 12 
 13 $ref: nvidia,tegra-pinmux-common.yaml
 14 
 15 properties:
 16   nvidia,function:
 17     enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2,
 18             eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3,
 19             pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi,
 20             sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte,
 21             usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,
 22             i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
 23             dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4,
 24             ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb,
 25             displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3,
 26             tsc_alt, istctrl, vi1_alt, dspk1, igpu ]
 27 
 28   # out of the common properties, only these are allowed for Tegra234
 29   nvidia,pins: true
 30   nvidia,pull: true
 31   nvidia,tristate: true
 32   nvidia,schmitt: true
 33   nvidia,enable-input: true
 34   nvidia,open-drain: true
 35   nvidia,lock: true
 36   nvidia,drive-type: true
 37   nvidia,io-hv: true
 38 
 39 required:
 40   - nvidia,pins
 41 
 42 # We would typically use unevaluatedProperties here but that has the
 43 # downside that all the properties in the common bindings become valid
 44 # for all chip generations. In this case, however, we want the per-SoC
 45 # bindings to be able to override which of the common properties are
 46 # allowed, since not all pinmux generations support the same sets of
 47 # properties. This way, the common bindings define the format of the
 48 # properties but the per-SoC bindings define which of them apply to a
 49 # given chip.
 50 additionalProperties: false
 51 
 52 ...

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