1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra30 pinmux Controller
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 properties:
14 compatible:
15 const: nvidia,tegra30-pinmux
16
17 reg:
18 items:
19 - description: pad control registers
20 - description: mux registers
21
22 patternProperties:
23 "^pinmux(-[a-z0-9-_]+)?$":
24 type: object
25
26 # pin groups
27 additionalProperties:
28 $ref: nvidia,tegra-pinmux-common.yaml
29 additionalProperties: false
30 properties:
31 nvidia,pins:
32 items:
33 enum: [ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2,
34 dap2_sclk_pa3, dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6,
35 sdmmc3_cmd_pa7, gmi_a17_pb0, gmi_a18_pb1, lcd_pwr0_pb2,
36 lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
37 sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0,
38 lcd_pwr1_pc1, uart2_txd_pc2, uart2_rxd_pc3,
39 gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, lcd_pwr2_pc6,
40 gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1,
41 lcd_dc1_pd2, sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5,
42 vi_vsync_pd6, vi_hsync_pd7, lcd_d0_pe0, lcd_d1_pe1,
43 lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, lcd_d6_pe6,
44 lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2,
45 lcd_d11_pf3, lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6,
46 lcd_d15_pf7, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
47 gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
48 gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
49 gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
50 gmi_ad15_ph7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2,
51 gmi_cs6_n_pi3, gmi_rst_n_pi4, gmi_iordy_pi5, gmi_cs7_n_pi6,
52 gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, gmi_cs1_n_pj2,
53 lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
54 uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1,
55 gmi_cs4_n_pk2, gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5,
56 spdif_in_pk6, gmi_a19_pk7, vi_d2_pl0, vi_d3_pl1, vi_d4_pl2,
57 vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, vi_d8_pl6, vi_d9_pl7,
58 lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
59 lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7,
60 dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3,
61 lcd_cs0_n_pn4, lcd_sdout_pn5, lcd_dc0_pn6, hdmi_int_pn7,
62 ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
63 ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5,
64 ulpi_data5_po6, ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1,
65 dap3_dout_pp2, dap3_sclk_pp3, dap4_fs_pp4, dap4_din_pp5,
66 dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, kb_col1_pq1,
67 kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
68 kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1,
69 kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5,
70 kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, kb_row9_ps1,
71 kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, kb_row13_ps5,
72 kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
73 vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5,
74 gen2_i2c_sda_pt6, sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4,
75 pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4,
76 ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, lcd_cs1_n_pw0,
77 lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
78 clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0,
79 spi2_miso_px1, spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4,
80 spi1_sck_px5, spi1_cs0_n_px6, spi1_miso_px7, ulpi_clk_py0,
81 ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, sdmmc1_dat3_py4,
82 sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
83 sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3,
84 lcd_sck_pz4, sys_clk_req_pz5, pwr_i2c_scl_pz6,
85 pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1,
86 sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
87 sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
88 cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
89 pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3,
90 sdmmc4_clk_pcc4, clk2_req_pcc5, pex_l2_rst_n_pcc6,
91 pex_l2_clkreq_n_pcc7, pex_l0_prsnt_n_pdd0,
92 pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3,
93 pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
94 pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0,
95 clk3_req_pee1, clk1_req_pee2, hdmi_cec_pee3, clk_32k_in,
96 core_pwr_req, cpu_pwr_req, owr, pwr_int_n,
97 # drive groups
98 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
99 drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_cec,
100 drive_crt, drive_csus, drive_dap1, drive_dap2, drive_dap3,
101 drive_dap4, drive_dbg, drive_ddc, drive_dev3, drive_gma,
102 drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_gmf,
103 drive_gmg, drive_gmh, drive_gpv, drive_lcd1, drive_lcd2,
104 drive_owr, drive_sdio1, drive_sdio2, drive_sdio3,
105 drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
106 drive_uda, drive_vi1 ]
107
108 nvidia,function:
109 enum: [ blink, cec, clk_12m_out, clk_32k_in, core_pwr_req,
110 cpu_pwr_req, crt, dap, ddr, dev3, displaya, displayb, dtv,
111 extperiph1, extperiph2, extperiph3, gmi, gmi_alt, hda, hdcp,
112 hdmi, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2,
113 i2s3, i2s4, invalid, kbc, mio, nand, nand_alt, owr, pcie,
114 pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, rsvd3,
115 rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif,
116 spi1, spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test,
117 trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2,
118 vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt2, vi_alt3 ]
119
120 nvidia,pull: true
121 nvidia,tristate: true
122 nvidia,schmitt: true
123 nvidia,pull-down-strength: true
124 nvidia,pull-up-strength: true
125 nvidia,high-speed-mode: true
126 nvidia,low-power-mode: true
127 nvidia,enable-input: true
128 nvidia,open-drain: true
129 nvidia,lock: true
130 nvidia,io-reset: true
131 nvidia,slew-rate-rising: true
132 nvidia,slew-rate-falling: true
133
134 required:
135 - nvidia,pins
136
137 additionalProperties: false
138
139 required:
140 - compatible
141 - reg
142
143 examples:
144 - |
145 pinctrl@70000000 {
146 compatible = "nvidia,tegra30-pinmux";
147 reg = <0x70000868 0x0d0>, /* Pad control registers */
148 <0x70003000 0x3e0>; /* Mux registers */
149
150 pinmux {
151 sdmmc4_clk_pcc4 {
152 nvidia,pins = "sdmmc4_clk_pcc4",
153 "sdmmc4_rst_n_pcc3";
154 nvidia,function = "sdmmc4";
155 nvidia,pull = <0>;
156 nvidia,tristate = <0>;
157 };
158
159 sdmmc4_dat0_paa0 {
160 nvidia,pins = "sdmmc4_dat0_paa0",
161 "sdmmc4_dat1_paa1",
162 "sdmmc4_dat2_paa2",
163 "sdmmc4_dat3_paa3",
164 "sdmmc4_dat4_paa4",
165 "sdmmc4_dat5_paa5",
166 "sdmmc4_dat6_paa6",
167 "sdmmc4_dat7_paa7";
168 nvidia,function = "sdmmc4";
169 nvidia,pull = <2>;
170 nvidia,tristate = <0>;
171 };
172 };
173 };
174 ...
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