1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8996-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm MSM8996 TLMM pin controller
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13 description:
14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC.
15
16 properties:
17 compatible:
18 const: qcom,msm8996-pinctrl
19
20 reg:
21 maxItems: 1
22
23 interrupts:
24 maxItems: 1
25
26 gpio-reserved-ranges:
27 minItems: 1
28 maxItems: 75
29
30 gpio-line-names:
31 maxItems: 150
32
33 patternProperties:
34 "-state$":
35 oneOf:
36 - $ref: "#/$defs/qcom-msm8996-tlmm-state"
37 - patternProperties:
38 "-pins$":
39 $ref: "#/$defs/qcom-msm8996-tlmm-state"
40 additionalProperties: false
41
42 $defs:
43 qcom-msm8996-tlmm-state:
44 type: object
45 description:
46 Pinctrl node's client devices use subnodes for desired pin configuration.
47 Client device subnodes use below standard properties.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49 unevaluatedProperties: false
50
51 properties:
52 pins:
53 description:
54 List of gpio pins affected by the properties specified in this
55 subnode.
56 items:
57 oneOf:
58 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
59 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
60 sdc2_cmd, sdc2_data ]
61 minItems: 1
62 maxItems: 36
63
64 function:
65 description:
66 Specify the alternative function to be configured for the specified
67 pins.
68
69 enum: [ gpio, blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
70 bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
71 qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
72 dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
73 blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
74 mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
75 atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio,
76 atest_char, cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8,
77 qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4,
78 atest_usb2, cci_i2c, qdss_stm3, dac_calib3, atest_usb23,
79 atest_char3, dac_calib4, qdss_stm2, atest_usb22, atest_char2,
80 qdss_stm1, dac_calib5, atest_usb21, atest_char1, dbg_out,
81 qdss_stm0, dac_calib6, atest_usb20, atest_char0, dac_calib10,
82 qdss_stm10, qdss_cti_trig_in_a, cci_timer4, blsp_spi6,
83 blsp_uart6, blsp_uim6, blsp2_spi, qdss_stm9,
84 qdss_cti_trig_out_a, dac_calib11, qdss_stm8, cci_timer0,
85 qdss_stm13, dac_calib7, cci_timer1, qdss_stm12, dac_calib8,
86 cci_timer2, blsp1_spi, qdss_stm11, dac_calib9, cci_timer3,
87 cci_async, dac_calib12, blsp_i2c6, qdss_tracectl_a,
88 dac_calib13, qdss_traceclk_a, dac_calib14, dac_calib15,
89 hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, dac_calib17,
90 hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, dac_calib19,
91 hdmi_hot, dac_calib20, dac_calib21, pci_e0, dac_calib22,
92 dac_calib23, dac_calib24, tsif1_sync, dac_calib25, sd_write,
93 tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti,
94 blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, uim3,
95 blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
96 blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
97 qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11,
98 blsp_uart11, blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a,
99 blsp_i2c11, cri_trng0, cri_trng1, cri_trng, qdss_stm18,
100 pri_mi2s, qdss_stm17, blsp_spi4, blsp_uart4, blsp_uim4,
101 qdss_stm16, qdss_stm15, blsp_i2c4, qdss_stm14, dac_calib26,
102 spkr_i2s, audio_ref, lpass_slimbus, isense_dbg, tsense_pwm1,
103 tsense_pwm2, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_stm21,
104 qdss_stm20, qdss_stm19, gcc_gp1_clk_b, sec_mi2s, blsp_spi5,
105 blsp_uart5, blsp_uim5, gcc_gp2_clk_b, gcc_gp3_clk_b, blsp_i2c5,
106 blsp_spi12, blsp_uart12, blsp_uim12, qdss_stm25, qdss_stm31,
107 blsp_i2c12, qdss_stm30, qdss_stm29, tsif1_clk, qdss_stm28,
108 tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b,
109 tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, sdc4_clk,
110 qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
111 sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
112 ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b,
113 blsp11_uart_rx_b, blsp11_i2c_sda_b, prng_rosc,
114 blsp11_i2c_scl_b, uim2, uim1, uim_batt, pci_e2, pa_indicator,
115 adsp_ext, ddr_bist, qdss_tracedata_11, qdss_tracedata_12,
116 modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, qspi_cs, ssbi2,
117 ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3 ]
118
119 required:
120 - pins
121
122 allOf:
123 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
124
125 required:
126 - compatible
127 - reg
128
129 unevaluatedProperties: false
130
131 examples:
132 - |
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
134
135 tlmm: pinctrl@1010000 {
136 compatible = "qcom,msm8996-pinctrl";
137 reg = <0x01010000 0x300000>;
138 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
139 gpio-controller;
140 gpio-ranges = <&tlmm 0 0 150>;
141 #gpio-cells = <2>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
144
145 blsp1-spi1-default-state {
146 spi-pins {
147 pins = "gpio0", "gpio1", "gpio3";
148 function = "blsp_spi1";
149 drive-strength = <12>;
150 bias-disable;
151 };
152
153 cs-pins {
154 pins = "gpio2";
155 function = "gpio";
156 drive-strength = <16>;
157 bias-disable;
158 output-high;
159 };
160 };
161
162 blsp1-spi1-sleep-state {
163 pins = "gpio0", "gpio1", "gpio2", "gpio3";
164 function = "gpio";
165 drive-strength = <2>;
166 bias-pull-down;
167 };
168 };
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