1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm MSM8998 TLMM pin controller
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13 description:
14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC.
15
16 properties:
17 compatible:
18 const: qcom,msm8998-pinctrl
19
20 reg:
21 maxItems: 1
22
23 interrupts:
24 maxItems: 1
25
26 gpio-reserved-ranges:
27 minItems: 1
28 maxItems: 75
29
30 gpio-line-names:
31 maxItems: 150
32
33 patternProperties:
34 "-state$":
35 oneOf:
36 - $ref: "#/$defs/qcom-msm8998-tlmm-state"
37 - patternProperties:
38 "-pins$":
39 $ref: "#/$defs/qcom-msm8998-tlmm-state"
40 additionalProperties: false
41
42 $defs:
43 qcom-msm8998-tlmm-state:
44 type: object
45 description:
46 Pinctrl node's client devices use subnodes for desired pin configuration.
47 Client device subnodes use below standard properties.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49 unevaluatedProperties: false
50
51 properties:
52 pins:
53 description:
54 List of gpio pins affected by the properties specified in this
55 subnode.
56 items:
57 oneOf:
58 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
59 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
60 minItems: 1
61 maxItems: 36
62
63 function:
64 description:
65 Specify the alternative function to be configured for the specified
66 pins.
67
68 enum: [ gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
69 atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
70 atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref,
71 bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b,
72 blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi,
73 blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
74 blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9,
75 blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2,
76 blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
77 blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12,
78 blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b,
79 blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b,
80 blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a,
81 blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a,
82 blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a,
83 blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a,
84 blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async,
85 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
86 cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
87 edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b,
88 gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
89 isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
90 m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
91 mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
92 nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
93 pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
94 pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
95 qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request,
96 qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43,
97 sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq,
98 ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0,
99 tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
100 uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
101 vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
102 wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
103
104 required:
105 - pins
106
107 allOf:
108 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
109
110 required:
111 - compatible
112 - reg
113
114 unevaluatedProperties: false
115
116 examples:
117 - |
118 #include <dt-bindings/interrupt-controller/arm-gic.h>
119
120 tlmm: pinctrl@3400000 {
121 compatible = "qcom,msm8998-pinctrl";
122 reg = <0x03400000 0xc00000>;
123 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
124 gpio-ranges = <&tlmm 0 0 150>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 gpio-reserved-ranges = <0 4>, <81 4>;
130
131 sdc2-off-state {
132 clk-pins {
133 pins = "sdc2_clk";
134 drive-strength = <2>;
135 bias-disable;
136 };
137
138 cmd-pins {
139 pins = "sdc2_cmd";
140 drive-strength = <2>;
141 bias-pull-up;
142 };
143
144 data-pins {
145 pins = "sdc2_data";
146 drive-strength = <2>;
147 bias-pull-up;
148 };
149 };
150
151 sdc2-cd-state {
152 pins = "gpio95";
153 function = "gpio";
154 bias-pull-up;
155 drive-strength = <2>;
156 };
157 };
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