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Linux/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Qualcomm SDM845 TLMM pin controller
  8 
  9 maintainers:
 10   - Bjorn Andersson <andersson@kernel.org>
 11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 12 
 13 description:
 14   Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
 15 
 16 allOf:
 17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 18 
 19 properties:
 20   compatible:
 21     const: qcom,sdm845-pinctrl
 22 
 23   reg:
 24     maxItems: 1
 25 
 26   interrupts:
 27     maxItems: 1
 28 
 29   gpio-reserved-ranges:
 30     minItems: 1
 31     maxItems: 75
 32 
 33   gpio-line-names:
 34     maxItems: 150
 35 
 36 patternProperties:
 37   "-state$":
 38     oneOf:
 39       - $ref: "#/$defs/qcom-sdm845-tlmm-state"
 40       - patternProperties:
 41           "-pins$":
 42             $ref: "#/$defs/qcom-sdm845-tlmm-state"
 43         additionalProperties: false
 44 
 45   "-hog(-[0-9]+)?$":
 46     type: object
 47     required:
 48       - gpio-hog
 49 
 50 $defs:
 51   qcom-sdm845-tlmm-state:
 52     type: object
 53     description:
 54       Pinctrl node's client devices use subnodes for desired pin configuration.
 55       Client device subnodes use below standard properties.
 56     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
 57     unevaluatedProperties: false
 58 
 59     properties:
 60       pins:
 61         description:
 62           List of gpio pins affected by the properties specified in this
 63           subnode.
 64         items:
 65           oneOf:
 66             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
 67             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
 68         minItems: 1
 69         maxItems: 36
 70 
 71       function:
 72         description:
 73           Specify the alternative function to be configured for the specified
 74           pins.
 75         enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
 76                 atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
 77                 atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
 78                 audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
 79                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
 80                 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
 81                 ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
 82                 gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
 83                 lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
 84                 mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
 85                 pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
 86                 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
 87                 qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
 88                 qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
 89                 qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
 90                 sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
 91                 spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
 92                 tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
 93                 tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
 94                 tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
 95                 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
 96                 uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
 97                 wlan1_adc1, wlan2_adc0, wlan2_adc1]
 98 
 99     required:
100       - pins
101 
102 required:
103   - compatible
104   - reg
105 
106 unevaluatedProperties: false
107 
108 examples:
109   - |
110     #include <dt-bindings/gpio/gpio.h>
111     #include <dt-bindings/interrupt-controller/arm-gic.h>
112 
113     pinctrl@3400000 {
114         compatible = "qcom,sdm845-pinctrl";
115         reg = <0x03400000 0xc00000>;
116         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
117         gpio-controller;
118         #gpio-cells = <2>;
119         interrupt-controller;
120         #interrupt-cells = <2>;
121         gpio-ranges = <&tlmm 0 0 151>;
122         wakeup-parent = <&pdc_intc>;
123 
124         ap-suspend-l-hog {
125             gpio-hog;
126             gpios = <126 GPIO_ACTIVE_LOW>;
127             output-low;
128         };
129 
130         cci0-default-state {
131             pins = "gpio17", "gpio18";
132             function = "cci_i2c";
133 
134             bias-pull-up;
135             drive-strength = <2>;
136         };
137 
138         cam0-default-state {
139             rst-pins {
140                 pins = "gpio9";
141                 function = "gpio";
142 
143                 drive-strength = <16>;
144                 bias-disable;
145             };
146 
147             mclk0-pins {
148                 pins = "gpio13";
149                 function = "cam_mclk";
150 
151                 drive-strength = <16>;
152                 bias-disable;
153             };
154         };
155     };

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