1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Technologies, Inc. SM4450 TLMM block
8
9 maintainers:
10 - Tengfei Fan <quic_tengfan@quicinc.com>
11
12 description:
13 Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.
14
15 allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18 properties:
19 compatible:
20 const: qcom,sm4450-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts: true
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
29
30 gpio-reserved-ranges:
31 minItems: 1
32 maxItems: 68
33
34 gpio-line-names:
35 maxItems: 136
36
37 "#gpio-cells": true
38 gpio-ranges: true
39 wakeup-parent: true
40
41 patternProperties:
42 "-state$":
43 oneOf:
44 - $ref: "#/$defs/qcom-sm4450-tlmm-state"
45 - patternProperties:
46 "-pins$":
47 $ref: "#/$defs/qcom-sm4450-tlmm-state"
48 additionalProperties: false
49
50 $defs:
51 qcom-sm4450-tlmm-state:
52 type: object
53 description:
54 Pinctrl node's client devices use subnodes for desired pin configuration.
55 Client device subnodes use below standard properties.
56 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57 unevaluatedProperties: false
58
59 properties:
60 pins:
61 description:
62 List of gpio pins affected by the properties specified in this
63 subnode.
64 items:
65 oneOf:
66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
67 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
68 minItems: 1
69 maxItems: 36
70
71 function:
72 description:
73 Specify the alternative function to be configured for the specified
74 pins.
75 enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk,
76 cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx,
77 coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist,
78 ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk,
79 gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1,
80 jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out,
81 mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav,
82 pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux,
83 prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio,
84 qlink0_enable, qlink0_request, qlink0_wmss_reset,
85 qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
86 qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3,
87 qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2,
88 tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
89 tgu_ch3_trigout, tmess_prng, tsense_pwm1_out,
90 tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps,
91 vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat,
92 wlan1_adc_dtest0, wlan1_adc_dtest1 ]
93
94 required:
95 - pins
96
97 required:
98 - compatible
99 - reg
100
101 additionalProperties: false
102
103 examples:
104 - |
105 #include <dt-bindings/interrupt-controller/arm-gic.h>
106 tlmm: pinctrl@f100000 {
107 compatible = "qcom,sm4450-tlmm";
108 reg = <0x0f100000 0x300000>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 gpio-ranges = <&tlmm 0 0 137>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
115
116 gpio-wo-state {
117 pins = "gpio1";
118 function = "gpio";
119 };
120
121 uart-w-state {
122 rx-pins {
123 pins = "gpio23";
124 function = "qup1_se2";
125 bias-pull-up;
126 };
127
128 tx-pins {
129 pins = "gpio22";
130 function = "qup1_se2";
131 bias-disable;
132 };
133 };
134 };
135 ...
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