1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Technologies, Inc. SM8250 TLMM block
8
9 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12 description:
13 Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
14
15 properties:
16 compatible:
17 const: qcom,sm8250-pinctrl
18
19 reg:
20 maxItems: 3
21
22 reg-names:
23 items:
24 - const: west
25 - const: south
26 - const: north
27
28 interrupts:
29 maxItems: 1
30
31 gpio-reserved-ranges:
32 minItems: 1
33 maxItems: 90
34
35 gpio-line-names:
36 maxItems: 180
37
38 patternProperties:
39 "-state$":
40 oneOf:
41 - $ref: "#/$defs/qcom-sm8250-tlmm-state"
42 - patternProperties:
43 "-pins$":
44 $ref: "#/$defs/qcom-sm8250-tlmm-state"
45 additionalProperties: false
46
47 $defs:
48 qcom-sm8250-tlmm-state:
49 type: object
50 description:
51 Pinctrl node's client devices use subnodes for desired pin configuration.
52 Client device subnodes use below standard properties.
53 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54 unevaluatedProperties: false
55
56 properties:
57 pins:
58 description:
59 List of gpio pins affected by the properties specified in this
60 subnode.
61 items:
62 oneOf:
63 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
64 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
65 minItems: 1
66 maxItems: 36
67
68 function:
69 description:
70 Specify the alternative function to be configured for the specified
71 pins.
72
73 enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
74 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
75 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
76 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
77 ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
78 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
79 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
80 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
81 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
82 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
83 qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
84 qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
85 qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
86 sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
87 tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
88 tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
89 tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
90
91 required:
92 - pins
93
94 allOf:
95 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
96
97 required:
98 - compatible
99 - reg
100 - reg-names
101
102 unevaluatedProperties: false
103
104 examples:
105 - |
106 #include <dt-bindings/interrupt-controller/arm-gic.h>
107 pinctrl@1f00000 {
108 compatible = "qcom,sm8250-pinctrl";
109 reg = <0x0f100000 0x300000>,
110 <0x0f500000 0x300000>,
111 <0x0f900000 0x300000>;
112 reg-names = "west", "south", "north";
113 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
114 gpio-controller;
115 #gpio-cells = <2>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
118 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
119 wakeup-parent = <&pdc>;
120 };
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