1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
8
9 maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
12 description:
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
15
16 properties:
17 compatible:
18 const: qcom,sm8450-lpass-lpi-pinctrl
19
20 reg:
21 items:
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
24
25 clocks:
26 items:
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
29
30 clock-names:
31 items:
32 - const: core
33 - const: audio
34
35 patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-sm8450-lpass-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-sm8450-lpass-state"
42 additionalProperties: false
43
44 $defs:
45 qcom-sm8450-lpass-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
60
61 function:
62 enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
63 dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
64 dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
65 qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
66 i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
67 wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
68 slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
69 ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
70 ext_mclk1_e ]
71 description:
72 Specify the alternative function to be configured for the specified
73 pins.
74
75 allOf:
76 - $ref: qcom,lpass-lpi-common.yaml#
77
78 required:
79 - compatible
80 - reg
81 - clocks
82 - clock-names
83
84 unevaluatedProperties: false
85
86 examples:
87 - |
88 #include <dt-bindings/sound/qcom,q6afe.h>
89 pinctrl@3440000 {
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
91 reg = <0x3440000 0x20000>,
92 <0x34d0000 0x10000>;
93 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
94 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
95 clock-names = "core", "audio";
96 gpio-controller;
97 #gpio-cells = <2>;
98 gpio-ranges = <&lpi_tlmm 0 0 23>;
99
100 wsa-swr-active-state {
101 clk-pins {
102 pins = "gpio10";
103 function = "wsa_swr_clk";
104 drive-strength = <2>;
105 slew-rate = <1>;
106 bias-disable;
107 };
108
109 data-pins {
110 pins = "gpio11";
111 function = "wsa_swr_data";
112 drive-strength = <2>;
113 slew-rate = <1>;
114 };
115 };
116
117 tx-swr-sleep-clk-state {
118 pins = "gpio0";
119 function = "swr_tx_clk";
120 drive-strength = <2>;
121 bias-pull-down;
122 };
123 };
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