1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Technologies, Inc. SM8550 TLMM block
8
9 maintainers:
10 - Abel Vesa <abel.vesa@linaro.org>
11
12 description:
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
14
15 allOf:
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18 properties:
19 compatible:
20 const: qcom,sm8550-tlmm
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 gpio-reserved-ranges:
29 minItems: 1
30 maxItems: 105
31
32 gpio-line-names:
33 maxItems: 210
34
35 patternProperties:
36 "-state$":
37 oneOf:
38 - $ref: "#/$defs/qcom-sm8550-tlmm-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-sm8550-tlmm-state"
42 additionalProperties: false
43
44 $defs:
45 qcom-sm8550-tlmm-state:
46 type: object
47 description:
48 Pinctrl node's client devices use subnodes for desired pin configuration.
49 Client device subnodes use below standard properties.
50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51 unevaluatedProperties: false
52
53 properties:
54 pins:
55 description:
56 List of gpio pins affected by the properties specified in this
57 subnode.
58 items:
59 oneOf:
60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62 minItems: 1
63 maxItems: 36
64
65 function:
66 description:
67 Specify the alternative function to be configured for the specified
68 pins.
69 enum: [ aon_cci, aoss_cti, atest_char, atest_usb,
70 audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk,
71 cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl,
72 cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx,
73 coex_uart1_tx, coex_uart2_rx, coex_uart2_tx,
74 cri_trng, dbg_out_clk, ddr_bist_complete,
75 ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
76 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot,
77 gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0,
78 i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
79 i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
80 i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck,
81 i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws,
82 ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out,
83 mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
84 mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
85 pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
86 pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
87 prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
88 qlink0_enable, qlink0_request, qlink0_wmss,
89 qlink1_enable, qlink1_request, qlink1_wmss,
90 qlink2_enable, qlink2_request, qlink2_wmss,
91 qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs,
92 qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
93 qup1_se5, qup1_se6, qup1_se7, qup2_se0,
94 qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira,
95 qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb,
96 qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1,
97 qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
98 qup2_se7, sd_write_protect, sdc40, sdc41, sdc42,
99 sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
100 tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
101 tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
102 tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
103 uim0_clk, uim0_data, uim0_present, uim0_reset,
104 uim1_clk, uim1_data, uim1_present, uim1_reset,
105 usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ]
106
107 required:
108 - pins
109
110 required:
111 - compatible
112 - reg
113
114 unevaluatedProperties: false
115
116 examples:
117 - |
118 #include <dt-bindings/interrupt-controller/arm-gic.h>
119 tlmm: pinctrl@f100000 {
120 compatible = "qcom,sm8550-tlmm";
121 reg = <0x0f100000 0x300000>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 gpio-ranges = <&tlmm 0 0 211>;
125 interrupt-controller;
126 #interrupt-cells = <2>;
127 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
128
129 gpio-wo-state {
130 pins = "gpio1";
131 function = "gpio";
132 };
133
134 uart-w-state {
135 rx-pins {
136 pins = "gpio26";
137 function = "qup2_se7";
138 bias-pull-up;
139 };
140
141 tx-pins {
142 pins = "gpio27";
143 function = "qup2_se7";
144 bias-disable;
145 };
146 };
147 };
148 ...
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