1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
8
9 maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
13 description:
14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
15 GPIO controller.
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
19 Up to 8 different alternate function modes exist for each single pin.
20
21 properties:
22 compatible:
23 oneOf:
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
27 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28 - renesas,r9a08g045-pinctrl # RZ/G3S
29 - renesas,r9a09g057-pinctrl # RZ/V2H(P)
30
31 - items:
32 - enum:
33 - renesas,r9a07g054-pinctrl # RZ/V2L
34 - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
35
36 reg:
37 maxItems: 1
38
39 gpio-controller: true
40
41 '#gpio-cells':
42 const: 2
43 description:
44 The first cell contains the global GPIO port index, constructed using the
45 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
46 second cell represents consumer flag as mentioned in ../gpio/gpio.txt
47 E.g. "RZG2L_GPIO(39, 1)" for P39_1.
48
49 gpio-ranges:
50 maxItems: 1
51
52 interrupt-controller: true
53
54 '#interrupt-cells':
55 const: 2
56 description:
57 The first cell contains the global GPIO port index, constructed using the
58 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
59 second cell is used to specify the flag.
60 E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
61 being used as an interrupt.
62
63 clocks:
64 maxItems: 1
65
66 power-domains:
67 maxItems: 1
68
69 resets:
70 oneOf:
71 - items:
72 - description: GPIO_RSTN signal
73 - description: GPIO_PORT_RESETN signal
74 - description: GPIO_SPARE_RESETN signal
75 - items:
76 - description: PFC main reset
77 - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
78
79 additionalProperties:
80 anyOf:
81 - type: object
82 additionalProperties: false
83 allOf:
84 - $ref: pincfg-node.yaml#
85 - $ref: pinmux-node.yaml#
86
87 description:
88 Pin controller client devices use pin configuration subnodes (children
89 and grandchildren) for desired pin configuration.
90 Client device subnodes use below standard properties.
91
92 properties:
93 pinmux:
94 description:
95 Values are constructed from GPIO port number, pin number, and
96 alternate function configuration number using the RZG2L_PORT_PINMUX()
97 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
98 pins: true
99 drive-strength:
100 enum: [ 2, 4, 8, 12 ]
101 drive-strength-microamp:
102 enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700,
103 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000,
104 10000 ]
105 output-impedance-ohms:
106 enum: [ 33, 50, 66, 100 ]
107 power-source:
108 description: I/O voltage in millivolt.
109 enum: [ 1800, 2500, 3300 ]
110 slew-rate: true
111 gpio-hog: true
112 gpios: true
113 input: true
114 input-enable: true
115 output-enable: true
116 output-high: true
117 output-low: true
118 line-name: true
119 bias-disable: true
120 bias-pull-down: true
121 bias-pull-up: true
122 renesas,output-impedance:
123 description:
124 Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
125 property corresponds to register bit values that can be set in the PFC_IOLH_mn
126 register, which adjusts the drive strength value and is pin-dependent.
127 $ref: /schemas/types.yaml#/definitions/uint32
128 enum: [0, 1, 2, 3]
129
130 - type: object
131 additionalProperties:
132 $ref: "#/additionalProperties/anyOf/0"
133
134 allOf:
135 - $ref: pinctrl.yaml#
136
137 - if:
138 properties:
139 compatible:
140 contains:
141 const: renesas,r9a09g057-pinctrl
142 then:
143 properties:
144 resets:
145 maxItems: 2
146 else:
147 properties:
148 resets:
149 minItems: 3
150
151 required:
152 - compatible
153 - reg
154 - gpio-controller
155 - '#gpio-cells'
156 - gpio-ranges
157 - interrupt-controller
158 - '#interrupt-cells'
159 - clocks
160 - power-domains
161 - resets
162
163 examples:
164 - |
165 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
166 #include <dt-bindings/clock/r9a07g044-cpg.h>
167
168 pinctrl: pinctrl@11030000 {
169 compatible = "renesas,r9a07g044-pinctrl";
170 reg = <0x11030000 0x10000>;
171
172 gpio-controller;
173 #gpio-cells = <2>;
174 gpio-ranges = <&pinctrl 0 0 392>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
178 resets = <&cpg R9A07G044_GPIO_RSTN>,
179 <&cpg R9A07G044_GPIO_PORT_RESETN>,
180 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
181 power-domains = <&cpg>;
182
183 scif0_pins: serial0 {
184 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
185 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
186 };
187
188 i2c1_pins: i2c1 {
189 pins = "RIIC1_SDA", "RIIC1_SCL";
190 input-enable;
191 };
192
193 sd1-pwr-en-hog {
194 gpio-hog;
195 gpios = <RZG2L_GPIO(39, 2) 0>;
196 output-high;
197 line-name = "sd1_pwr_en";
198 };
199
200 sdhi1_pins: sd1 {
201 sd1_mux {
202 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
203 <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
204 power-source = <3300>;
205 };
206
207 sd1_data {
208 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
209 power-source = <3300>;
210 };
211
212 sd1_ctrl {
213 pins = "SD1_CLK", "SD1_CMD";
214 power-source = <3300>;
215 };
216 };
217 };
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