1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/V2M combined Pin and GPIO controller
8
9 maintainers:
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
12
13 description:
14 The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
15 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
16 Each port features up to 16 pins, each of them configurable for GPIO function
17 (port mode) or in alternate function mode.
18 Up to 8 different alternate function modes exist for each single pin.
19
20 properties:
21 compatible:
22 const: renesas,r9a09g011-pinctrl # RZ/V2M
23
24 reg:
25 maxItems: 1
26
27 gpio-controller: true
28
29 '#gpio-cells':
30 const: 2
31 description:
32 The first cell contains the global GPIO port index, constructed using the
33 RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
34 second cell represents consumer flag as mentioned in ../gpio/gpio.txt
35 E.g. "RZV2M_GPIO(8, 1)" for P8_1.
36
37 gpio-ranges:
38 maxItems: 1
39
40 interrupts:
41 description: INEXINT[0..38] corresponding to individual pin inputs.
42 maxItems: 39
43
44 clocks:
45 maxItems: 1
46
47 power-domains:
48 maxItems: 1
49
50 resets:
51 maxItems: 1
52
53 additionalProperties:
54 anyOf:
55 - type: object
56 additionalProperties: false
57 allOf:
58 - $ref: pincfg-node.yaml#
59 - $ref: pinmux-node.yaml#
60
61 description:
62 Pin controller client devices use pin configuration subnodes (children
63 and grandchildren) for desired pin configuration.
64 Client device subnodes use below standard properties.
65
66 properties:
67 pinmux:
68 description:
69 Values are constructed from GPIO port number, pin number, and
70 alternate function configuration number using the RZV2M_PORT_PINMUX()
71 helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
72 pins: true
73 bias-disable: true
74 bias-pull-down: true
75 bias-pull-up: true
76 drive-strength-microamp:
77 # Superset of supported values
78 enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
79 9000, 9600, 11000, 12000, 13000, 18000 ]
80 slew-rate:
81 description: 0 is slow slew rate, 1 is fast slew rate
82 enum: [ 0, 1 ]
83 gpio-hog: true
84 gpios: true
85 output-high: true
86 output-low: true
87 line-name: true
88
89 - type: object
90 additionalProperties:
91 $ref: "#/additionalProperties/anyOf/0"
92
93 allOf:
94 - $ref: pinctrl.yaml#
95
96 required:
97 - compatible
98 - reg
99 - gpio-controller
100 - '#gpio-cells'
101 - gpio-ranges
102 - interrupts
103 - clocks
104 - power-domains
105 - resets
106
107 examples:
108 - |
109 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
110 #include <dt-bindings/clock/r9a09g011-cpg.h>
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112
113 pinctrl: pinctrl@b6250000 {
114 compatible = "renesas,r9a09g011-pinctrl";
115 reg = <0xb6250000 0x800>;
116
117 gpio-controller;
118 #gpio-cells = <2>;
119 gpio-ranges = <&pinctrl 0 0 352>;
120 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
160 resets = <&cpg R9A09G011_PFC_PRESETN>;
161 power-domains = <&cpg>;
162
163 i2c2_pins: i2c2 {
164 pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
165 <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
166 };
167 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.