1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip Pinmux Controller
8
9 maintainers:
10 - Heiko Stuebner <heiko@sntech.de>
11
12 description: |
13 The Rockchip Pinmux Controller enables the IC to share one PAD
14 to several functional blocks. The sharing is done by multiplexing
15 the PAD input/output signals. For each PAD there are several muxing
16 options with option 0 being used as a GPIO.
17
18 Please refer to pinctrl-bindings.txt in this directory for details of the
19 common pinctrl bindings used by client devices, including the meaning of the
20 phrase "pin configuration node".
21
22 The Rockchip pin configuration node is a node of a group of pins which can be
23 used for a specific device or function. This node represents both mux and
24 config of the pins in that group. The 'pins' selects the function mode
25 (also named pin mode) this pin can work on and the 'config' configures
26 various pad settings such as pull-up, etc.
27
28 The pins are grouped into up to 9 individual pin banks which need to be
29 defined as gpio sub-nodes of the pinmux controller.
30
31 properties:
32 compatible:
33 enum:
34 - rockchip,px30-pinctrl
35 - rockchip,rk2928-pinctrl
36 - rockchip,rk3036-pinctrl
37 - rockchip,rk3066a-pinctrl
38 - rockchip,rk3066b-pinctrl
39 - rockchip,rk3128-pinctrl
40 - rockchip,rk3188-pinctrl
41 - rockchip,rk3228-pinctrl
42 - rockchip,rk3288-pinctrl
43 - rockchip,rk3308-pinctrl
44 - rockchip,rk3328-pinctrl
45 - rockchip,rk3368-pinctrl
46 - rockchip,rk3399-pinctrl
47 - rockchip,rk3568-pinctrl
48 - rockchip,rk3576-pinctrl
49 - rockchip,rk3588-pinctrl
50 - rockchip,rv1108-pinctrl
51 - rockchip,rv1126-pinctrl
52
53 rockchip,grf:
54 $ref: /schemas/types.yaml#/definitions/phandle
55 description:
56 The phandle of the syscon node for the GRF registers.
57
58 rockchip,pmu:
59 $ref: /schemas/types.yaml#/definitions/phandle
60 description:
61 The phandle of the syscon node for the PMU registers,
62 as some SoCs carry parts of the iomux controller registers there.
63 Required for at least rk3188 and rk3288. On the rk3368 this should
64 point to the PMUGRF syscon.
65
66 "#address-cells":
67 enum: [1, 2]
68
69 "#size-cells":
70 enum: [1, 2]
71
72 ranges: true
73
74 allOf:
75 - $ref: pinctrl.yaml#
76
77 required:
78 - compatible
79 - rockchip,grf
80
81 patternProperties:
82 "gpio@[0-9a-f]+$":
83 type: object
84
85 $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
86 deprecated: true
87
88 unevaluatedProperties: false
89
90 "pcfg-[a-z0-9-]+$":
91 type: object
92 properties:
93 bias-disable: true
94
95 bias-pull-down: true
96
97 bias-pull-pin-default: true
98
99 bias-pull-up: true
100
101 drive-strength:
102 minimum: 0
103 maximum: 20
104
105 input-enable: true
106
107 input-schmitt-enable: true
108
109 output-high: true
110
111 output-low: true
112
113 additionalProperties: false
114
115 additionalProperties:
116 type: object
117 additionalProperties:
118 type: object
119 additionalProperties: false
120
121 properties:
122 rockchip,pins:
123 $ref: /schemas/types.yaml#/definitions/uint32-matrix
124 minItems: 1
125 items:
126 items:
127 - minimum: 0
128 maximum: 8
129 description:
130 Pin bank.
131 - minimum: 0
132 maximum: 31
133 description:
134 Pin bank index.
135 - minimum: 0
136 maximum: 13
137 description:
138 Mux 0 means GPIO and mux 1 to N means
139 the specific device function.
140 - description:
141 The phandle of a node contains the generic pinconfig options
142 to use as described in pinctrl-bindings.txt.
143
144 examples:
145 - |
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/pinctrl/rockchip.h>
148
149 pinctrl: pinctrl {
150 compatible = "rockchip,rk3066a-pinctrl";
151 rockchip,grf = <&grf>;
152
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges;
156
157 gpio0: gpio@20034000 {
158 compatible = "rockchip,gpio-bank";
159 reg = <0x20034000 0x100>;
160 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&clk_gates8 9>;
162
163 gpio-controller;
164 #gpio-cells = <2>;
165
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 };
169
170 pcfg_pull_default: pcfg-pull-default {
171 bias-pull-pin-default;
172 };
173
174 uart2 {
175 uart2_xfer: uart2-xfer {
176 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
177 <1 RK_PB1 1 &pcfg_pull_default>;
178 };
179 };
180 };
181
182 uart2: serial@20064000 {
183 compatible = "snps,dw-apb-uart";
184 reg = <0x20064000 0x400>;
185 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&mux_uart2>;
187 pinctrl-0 = <&uart2_xfer>;
188 pinctrl-names = "default";
189 reg-io-width = <1>;
190 reg-shift = <2>;
191 };
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