1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Samsung S3C/S5P/Exynos SoC pin controller
8
9 maintainers:
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
13
14 description: |
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
16 controller.
17
18 All the pin controller nodes should be represented in the aliases node using
19 the following format 'pinctrl{n}' where n is a unique number for the alias.
20
21 The controller supports three types of interrupts::
22 - External GPIO interrupts (see interrupts property in pin controller node);
23
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
27
28 - External wake-up interrupts - direct (capable of waking up the system, see
29 interrupts property in every bank of pin controller with external wake-up
30 interrupt controller - samsung,pinctrl-gpio-bank.yaml).
31
32 properties:
33 $nodename:
34 pattern: "^pinctrl(@.*)?"
35
36 compatible:
37 enum:
38 - google,gs101-pinctrl
39 - samsung,s3c2412-pinctrl
40 - samsung,s3c2416-pinctrl
41 - samsung,s3c2440-pinctrl
42 - samsung,s3c2450-pinctrl
43 - samsung,s3c64xx-pinctrl
44 - samsung,s5pv210-pinctrl
45 - samsung,exynos3250-pinctrl
46 - samsung,exynos4210-pinctrl
47 - samsung,exynos4x12-pinctrl
48 - samsung,exynos5250-pinctrl
49 - samsung,exynos5260-pinctrl
50 - samsung,exynos5410-pinctrl
51 - samsung,exynos5420-pinctrl
52 - samsung,exynos5433-pinctrl
53 - samsung,exynos7-pinctrl
54 - samsung,exynos7885-pinctrl
55 - samsung,exynos850-pinctrl
56 - samsung,exynosautov9-pinctrl
57 - samsung,exynosautov920-pinctrl
58 - tesla,fsd-pinctrl
59
60 interrupts:
61 description:
62 Required for GPIO banks supporting external GPIO interrupts.
63 maxItems: 1
64
65 power-domains:
66 maxItems: 1
67
68 reg:
69 description:
70 Second base address of the pin controller if the specific registers of
71 the pin controller are separated into the different base address.
72 Only certain banks of certain pin controller might need it.
73 minItems: 1
74 maxItems: 2
75
76 clocks:
77 maxItems: 1
78
79 clock-names:
80 items:
81 - const: pclk
82
83 wakeup-interrupt-controller:
84 $ref: samsung,pinctrl-wakeup-interrupt.yaml
85
86 patternProperties:
87 "^[a-z]+[0-9]*-gpio-bank$":
88 description:
89 Pin banks of the controller are represented by child nodes of the
90 controller node. Bank name is taken from name of the node.
91 $ref: samsung,pinctrl-gpio-bank.yaml
92
93 "^[a-z0-9-]+-pins$":
94 oneOf:
95 - $ref: samsung,pinctrl-pins-cfg.yaml
96 required:
97 - samsung,pins
98 - type: object
99 patternProperties:
100 "^[a-z0-9-]+-pins$":
101 $ref: samsung,pinctrl-pins-cfg.yaml
102
103 additionalProperties: false
104
105 "^(initial|sleep)-state$":
106 type: object
107 additionalProperties: false
108
109 patternProperties:
110 "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
111 $ref: samsung,pinctrl-pins-cfg.yaml
112
113 properties:
114 samsung,pins:
115 description: See samsung,pinctrl-pins-cfg.yaml
116 $ref: /schemas/types.yaml#/definitions/string-array
117 maxItems: 1
118
119 required:
120 - samsung,pins
121
122 unevaluatedProperties: false
123
124 required:
125 - compatible
126 - reg
127
128 allOf:
129 - $ref: pinctrl.yaml#
130 - if:
131 properties:
132 compatible:
133 contains:
134 const: google,gs101-pinctrl
135 then:
136 required:
137 - clocks
138 - clock-names
139 else:
140 properties:
141 clocks: false
142 clock-names: false
143
144 - if:
145 properties:
146 compatible:
147 contains:
148 const: samsung,exynos5433-pinctrl
149 then:
150 properties:
151 reg:
152 minItems: 1
153 maxItems: 2
154 else:
155 properties:
156 reg:
157 minItems: 1
158 maxItems: 1
159
160 additionalProperties: false
161
162 examples:
163 - |
164 pinctrl@7f008000 {
165 compatible = "samsung,s3c64xx-pinctrl";
166 reg = <0x7f008000 0x1000>;
167 interrupt-parent = <&vic1>;
168 interrupts = <21>;
169
170 wakeup-interrupt-controller {
171 compatible = "samsung,s3c64xx-wakeup-eint";
172 interrupts-extended = <&vic0 0>,
173 <&vic0 1>,
174 <&vic1 0>,
175 <&vic1 1>;
176 };
177
178 /* Pin bank with external GPIO or muxed external wake-up interrupts */
179 gpa-gpio-bank {
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 // ...
187
188 uart0-data-pins {
189 samsung,pins = "gpa-0", "gpa-1";
190 samsung,pin-function = <2>;
191 samsung,pin-pud = <0>;
192 };
193
194 // ...
195 };
196
197 - |
198 #include <dt-bindings/interrupt-controller/arm-gic.h>
199
200 pinctrl@11400000 {
201 compatible = "samsung,exynos4210-pinctrl";
202 reg = <0x11400000 0x1000>;
203 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
204
205 pinctrl-names = "default";
206 pinctrl-0 = <&sleep0>;
207
208 /* Pin bank with external GPIO or muxed external wake-up interrupts */
209 gpa0-gpio-bank {
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 // ...
217
218 uart0-data-pins {
219 samsung,pins = "gpa0-0", "gpa0-1";
220 samsung,pin-function = <2>;
221 samsung,pin-pud = <0>;
222 samsung,pin-drv = <0>;
223 };
224
225 // ...
226
227 sleep0: sleep-state {
228 gpa0-0-pin {
229 samsung,pins = "gpa0-0";
230 samsung,pin-con-pdn = <2>;
231 samsung,pin-pud-pdn = <0>;
232 };
233
234 gpa0-1-pin {
235 samsung,pins = "gpa0-1";
236 samsung,pin-con-pdn = <0>;
237 samsung,pin-pud-pdn = <0>;
238 };
239
240 // ...
241 };
242 };
243
244 - |
245 #include <dt-bindings/interrupt-controller/arm-gic.h>
246
247 pinctrl@11000000 {
248 compatible = "samsung,exynos4210-pinctrl";
249 reg = <0x11000000 0x1000>;
250 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
251
252 wakeup-interrupt-controller {
253 compatible = "samsung,exynos4210-wakeup-eint";
254 interrupt-parent = <&gic>;
255 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
256 };
257
258 /* Pin bank with external GPIO or muxed external wake-up interrupts */
259 gpj0-gpio-bank {
260 gpio-controller;
261 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265
266 /* Pin bank without external interrupts */
267 gpy0-gpio-bank {
268 gpio-controller;
269 #gpio-cells = <2>;
270 };
271
272 /* Pin bank with external direct wake-up interrupts */
273 gpx0-gpio-bank {
274 gpio-controller;
275 #gpio-cells = <2>;
276
277 interrupt-controller;
278 interrupt-parent = <&gic>;
279 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
287 #interrupt-cells = <2>;
288 };
289
290 // ...
291
292 sd0-clk-pins {
293 samsung,pins = "gpk0-0";
294 samsung,pin-function = <2>;
295 samsung,pin-pud = <0>;
296 samsung,pin-drv = <3>;
297 };
298
299 sd4-bus-width8-pins {
300 part-1-pins {
301 samsung,pins = "gpk0-3", "gpk0-4",
302 "gpk0-5", "gpk0-6";
303 samsung,pin-function = <3>;
304 samsung,pin-pud = <3>;
305 samsung,pin-drv = <3>;
306 };
307
308 part-2-pins {
309 samsung,pins = "gpk1-3", "gpk1-4",
310 "gpk1-5", "gpk1-6";
311 samsung,pin-function = <4>;
312 samsung,pin-pud = <3>;
313 samsung,pin-drv = <3>;
314 };
315 };
316
317 // ...
318
319 otg-gp-pins {
320 samsung,pins = "gpx3-3";
321 samsung,pin-function = <1>;
322 samsung,pin-pud = <0>;
323 samsung,pin-drv = <0>;
324 samsung,pin-val = <0>;
325 };
326 };
327
328 - |
329 #include <dt-bindings/interrupt-controller/arm-gic.h>
330
331 pinctrl@10580000 {
332 compatible = "samsung,exynos5433-pinctrl";
333 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
334
335 pinctrl-names = "default";
336 pinctrl-0 = <&initial_alive>;
337
338 wakeup-interrupt-controller {
339 compatible = "samsung,exynos5433-wakeup-eint",
340 "samsung,exynos7-wakeup-eint";
341 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
342 };
343
344 /* Pin bank with external direct wake-up interrupts */
345 gpa0-gpio-bank {
346 gpio-controller;
347 #gpio-cells = <2>;
348
349 interrupt-controller;
350 interrupt-parent = <&gic>;
351 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
359 #interrupt-cells = <2>;
360 };
361
362 // ...
363
364 te-irq-pins {
365 samsung,pins = "gpf1-3";
366 samsung,pin-function = <0xf>;
367 };
368
369 // ..
370
371 initial_alive: initial-state {
372 gpa0-0-pin {
373 samsung,pins = "gpa0-0";
374 samsung,pin-function = <0>;
375 samsung,pin-pud = <1>;
376 samsung,pin-drv = <0>;
377 };
378
379 // ...
380 };
381 };
382
383 - |
384 #include <dt-bindings/interrupt-controller/arm-gic.h>
385
386 pinctrl@114b0000 {
387 compatible = "samsung,exynos5433-pinctrl";
388 reg = <0x114b0000 0x1000>;
389 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
390 power-domains = <&pd_aud>;
391
392 /* Pin bank with external GPIO or muxed external wake-up interrupts */
393 gpz0-gpio-bank {
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 // ...
401
402 i2s0-bus-pins {
403 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
404 "gpz0-4", "gpz0-5", "gpz0-6";
405 samsung,pin-function = <2>;
406 samsung,pin-pud = <0>;
407 samsung,pin-drv = <0>;
408 };
409
410 // ...
411 };
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