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Linux/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Freescale i.MX General Power Controller
  8 
  9 maintainers:
 10   - Philipp Zabel <p.zabel@pengutronix.de>
 11 
 12 description: |
 13   The i.MX6 General Power Control (GPC) block contains DVFS load tracking
 14   counters and Power Gating Control (PGC).
 15 
 16   The power domains are generic power domain providers as documented in
 17   Documentation/devicetree/bindings/power/power-domain.yaml. They are
 18   described as subnodes of the power gating controller 'pgc' node of the GPC.
 19 
 20   IP cores belonging to a power domain should contain a 'power-domains'
 21   property that is a phandle pointing to the power domain the device belongs
 22   to.
 23 
 24 properties:
 25   compatible:
 26     oneOf:
 27       - enum:
 28           - fsl,imx6q-gpc
 29       - items:
 30           - enum:
 31               - fsl,imx6qp-gpc
 32               - fsl,imx6sl-gpc
 33               - fsl,imx6sx-gpc
 34               - fsl,imx6ul-gpc
 35           - const: fsl,imx6q-gpc
 36 
 37   reg:
 38     maxItems: 1
 39 
 40   interrupts:
 41     maxItems: 1
 42 
 43   interrupt-controller: true
 44   '#interrupt-cells':
 45     const: 3
 46 
 47   clocks:
 48     maxItems: 1
 49 
 50   clock-names:
 51     const: ipg
 52 
 53   pgc:
 54     type: object
 55     additionalProperties: false
 56     description: list of power domains provided by this controller.
 57 
 58     properties:
 59       '#address-cells':
 60         const: 1
 61 
 62       '#size-cells':
 63         const: 0
 64 
 65     patternProperties:
 66       "power-domain@[0-9]$":
 67         type: object
 68         additionalProperties: false
 69 
 70         properties:
 71 
 72           '#power-domain-cells':
 73             const: 0
 74 
 75           reg:
 76             description: |
 77               The following DOMAIN_INDEX values are valid for i.MX6Q:
 78                 ARM_DOMAIN     0
 79                 PU_DOMAIN      1
 80               The following additional DOMAIN_INDEX value is valid for i.MX6SL:
 81                 DISPLAY_DOMAIN 2
 82               The following additional DOMAIN_INDEX value is valid for i.MX6SX:
 83                 PCI_DOMAIN     3
 84             maxItems: 1
 85 
 86           clocks:
 87             description: |
 88               A number of phandles to clocks that need to be enabled during domain
 89               power-up sequencing to ensure reset propagation into devices located
 90               inside this power domain.
 91             minItems: 1
 92             maxItems: 7
 93 
 94           power-supply: true
 95 
 96         required:
 97           - '#power-domain-cells'
 98           - reg
 99 
100     required:
101       - '#address-cells'
102       - '#size-cells'
103 
104 required:
105   - compatible
106   - reg
107   - interrupts
108   - clocks
109   - clock-names
110   - pgc
111 
112 additionalProperties: false
113 
114 examples:
115   - |
116     #include <dt-bindings/clock/imx6qdl-clock.h>
117     #include <dt-bindings/interrupt-controller/arm-gic.h>
118 
119     gpc@20dc000 {
120         compatible = "fsl,imx6q-gpc";
121         reg = <0x020dc000 0x4000>;
122         interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
123         clocks = <&clks IMX6QDL_CLK_IPG>;
124         clock-names = "ipg";
125 
126         pgc {
127             #address-cells = <1>;
128             #size-cells = <0>;
129 
130             power-domain@0 {
131                 reg = <0>;
132                 #power-domain-cells = <0>;
133             };
134 
135             pd_pu: power-domain@1 {
136                 reg = <1>;
137                 #power-domain-cells = <0>;
138                 power-supply = <&reg_pu>;
139                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
140                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
141                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
142                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
143                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
144                          <&clks IMX6QDL_CLK_VPU_AXI>;
145             };
146         };
147     };

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