1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Qualcomm SC7280 ADSP Peripheral Image Loader 8 9 maintainers: 10 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> 11 12 description: 13 This document describes the hardware for a component that loads and boots firmware 14 on the Qualcomm Technology Inc. ADSP. 15 16 properties: 17 compatible: 18 enum: 19 - qcom,sc7280-adsp-pil 20 21 reg: 22 items: 23 - description: qdsp6ss register 24 - description: efuse q6ss register 25 26 iommus: 27 items: 28 - description: Phandle to apps_smmu node with sid mask 29 30 interrupts: 31 items: 32 - description: Watchdog interrupt 33 - description: Fatal interrupt 34 - description: Ready interrupt 35 - description: Handover interrupt 36 - description: Stop acknowledge interrupt 37 - description: Shutdown acknowledge interrupt 38 39 interrupt-names: 40 items: 41 - const: wdog 42 - const: fatal 43 - const: ready 44 - const: handover 45 - const: stop-ack 46 - const: shutdown-ack 47 48 clocks: 49 items: 50 - description: XO clock 51 - description: GCC CFG NOC LPASS clock 52 53 clock-names: 54 items: 55 - const: xo 56 - const: gcc_cfg_noc_lpass 57 58 power-domains: 59 items: 60 - description: LCX power domain 61 62 resets: 63 items: 64 - description: PDC AUDIO SYNC RESET 65 - description: CC LPASS restart 66 67 reset-names: 68 items: 69 - const: pdc_sync 70 - const: cc_lpass 71 72 memory-region: 73 maxItems: 1 74 description: Reference to the reserved-memory for the Hexagon core 75 76 qcom,halt-regs: 77 $ref: /schemas/types.yaml#/definitions/phandle-array 78 description: 79 Phandle reference to a syscon representing TCSR followed by the 80 four offsets within syscon for q6, modem, nc and qv6 halt registers. 81 items: 82 - items: 83 - description: phandle to TCSR_MUTEX registers 84 - description: offset to the Q6 halt register 85 - description: offset to the modem halt register 86 - description: offset to the nc halt register 87 - description: offset to the vq6 halt register 88 89 qcom,smem-states: 90 $ref: /schemas/types.yaml#/definitions/phandle-array 91 description: States used by the AP to signal the Hexagon core 92 items: 93 - description: Stop the modem 94 95 qcom,smem-state-names: 96 description: The names of the state bits used for SMP2P output 97 const: stop 98 99 qcom,qmp: 100 $ref: /schemas/types.yaml#/definitions/phandle 101 description: Reference to the AOSS side-channel message RAM. 102 103 glink-edge: 104 $ref: qcom,glink-edge.yaml# 105 type: object 106 unevaluatedProperties: false 107 description: | 108 Qualcomm G-Link subnode which represents communication edge, channels 109 and devices related to the ADSP. 110 111 properties: 112 label: 113 const: lpass 114 115 gpr: true 116 apr: false 117 fastrpc: false 118 119 required: 120 - label 121 122 required: 123 - compatible 124 - reg 125 - interrupts 126 - interrupt-names 127 - clocks 128 - clock-names 129 - power-domains 130 - resets 131 - reset-names 132 - qcom,halt-regs 133 - memory-region 134 - qcom,smem-states 135 - qcom,smem-state-names 136 - qcom,qmp 137 138 additionalProperties: false 139 140 examples: 141 - | 142 #include <dt-bindings/interrupt-controller/arm-gic.h> 143 #include <dt-bindings/clock/qcom,rpmh.h> 144 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 145 #include <dt-bindings/clock/qcom,lpass-sc7280.h> 146 #include <dt-bindings/reset/qcom,sdm845-aoss.h> 147 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 148 #include <dt-bindings/power/qcom-rpmpd.h> 149 #include <dt-bindings/mailbox/qcom-ipcc.h> 150 151 remoteproc@3000000 { 152 compatible = "qcom,sc7280-adsp-pil"; 153 reg = <0x03000000 0x5000>, 154 <0x0355b000 0x10>; 155 156 interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>, 157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 158 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 159 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 160 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 161 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 162 163 interrupt-names = "wdog", "fatal", "ready", 164 "handover", "stop-ack", "shutdown-ack"; 165 166 clocks = <&rpmhcc RPMH_CXO_CLK>, 167 <&gcc GCC_CFG_NOC_LPASS_CLK>; 168 clock-names = "xo", "gcc_cfg_noc_lpass"; 169 170 power-domains = <&rpmhpd SC7280_LCX>; 171 172 resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, 173 <&aoss_reset AOSS_CC_LPASS_RESTART>; 174 reset-names = "pdc_sync", "cc_lpass"; 175 176 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 177 178 memory-region = <&adsp_mem>; 179 180 qcom,smem-states = <&adsp_smp2p_out 0>; 181 qcom,smem-state-names = "stop"; 182 183 qcom,qmp = <&aoss_qmp>; 184 185 glink-edge { 186 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 187 IPCC_MPROC_SIGNAL_GLINK_QMP 188 IRQ_TYPE_EDGE_RISING>; 189 mboxes = <&ipcc IPCC_CLIENT_LPASS 190 IPCC_MPROC_SIGNAL_GLINK_QMP>; 191 192 label = "lpass"; 193 qcom,remote-pid = <2>; 194 }; 195 };
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