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Linux/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt

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  1 TI SysCon Reset Controller
  2 =======================
  3 
  4 Almost all SoCs have hardware modules that require reset control in addition
  5 to clock and power control for their functionality. The reset control is
  6 typically provided by means of memory-mapped I/O registers. These registers are
  7 sometimes a part of a larger register space region implementing various
  8 functionalities. This register range is best represented as a syscon node to
  9 allow multiple entities to access their relevant registers in the common
 10 register space.
 11 
 12 A SysCon Reset Controller node defines a device that uses a syscon node
 13 and provides reset management functionality for various hardware modules
 14 present on the SoC.
 15 
 16 SysCon Reset Controller Node
 17 ============================
 18 Each of the reset provider/controller nodes should be a child of a syscon
 19 node and have the following properties.
 20 
 21 Required properties:
 22 --------------------
 23  - compatible           : Should be,
 24                             "ti,k2e-pscrst"
 25                             "ti,k2l-pscrst"
 26                             "ti,k2hk-pscrst"
 27                             "ti,syscon-reset"
 28  - #reset-cells         : Should be 1. Please see the reset consumer node below
 29                           for usage details
 30  - ti,reset-bits        : Contains the reset control register information
 31                           Should contain 7 cells for each reset exposed to
 32                           consumers, defined as:
 33                             Cell #1 : offset of the reset assert control
 34                                       register from the syscon register base
 35                             Cell #2 : bit position of the reset in the reset
 36                                       assert control register
 37                             Cell #3 : offset of the reset deassert control
 38                                       register from the syscon register base
 39                             Cell #4 : bit position of the reset in the reset
 40                                       deassert control register
 41                             Cell #5 : offset of the reset status register
 42                                       from the syscon register base
 43                             Cell #6 : bit position of the reset in the
 44                                       reset status register
 45                             Cell #7 : Flags used to control reset behavior,
 46                                       available flags defined in the DT include
 47                                       file <dt-bindings/reset/ti-syscon.h>
 48 
 49 SysCon Reset Consumer Nodes
 50 ===========================
 51 Each of the reset consumer nodes should have the following properties,
 52 in addition to their own properties.
 53 
 54 Required properties:
 55 --------------------
 56  - resets       : A phandle to the reset controller node and an index number
 57                   to a reset specifier as defined above.
 58 
 59 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
 60 common reset controller usage by consumers.
 61 
 62 Example:
 63 --------
 64 The following example demonstrates a syscon node, the reset controller node
 65 using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
 66 66AK2E SoC.
 67 
 68 / {
 69         soc {
 70                 psc: power-sleep-controller@2350000 {
 71                         compatible = "syscon", "simple-mfd";
 72                         reg = <0x02350000 0x1000>;
 73 
 74                         pscrst: reset-controller {
 75                                 compatible = "ti,k2e-pscrst", "ti,syscon-reset";
 76                                 #reset-cells = <1>;
 77 
 78                                 ti,reset-bits = <
 79                                         0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */
 80                                         0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */
 81                                 >;
 82                         };
 83                 };
 84 
 85                 dsp0: dsp0 {
 86                         ...
 87                         resets = <&pscrst 0>;
 88                         ...
 89                 };
 90         };
 91 };

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