1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: RISC-V CPUs
8
9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
13
14 description: |
15 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of which are listed here:
17
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthreads, could be described as
24 having four harts.
25
26 allOf:
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
29
30 properties:
31 compatible:
32 oneOf:
33 - items:
34 - enum:
35 - amd,mbv32
36 - andestech,ax45mp
37 - canaan,k210
38 - sifive,bullet0
39 - sifive,e5
40 - sifive,e7
41 - sifive,e71
42 - sifive,rocket0
43 - sifive,s7
44 - sifive,u5
45 - sifive,u54
46 - sifive,u7
47 - sifive,u74
48 - sifive,u74-mc
49 - thead,c906
50 - thead,c908
51 - thead,c910
52 - thead,c920
53 - const: riscv
54 - items:
55 - enum:
56 - sifive,e51
57 - sifive,u54-mc
58 - const: sifive,rocket0
59 - const: riscv
60 - const: riscv # Simulator only
61 description:
62 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart.
64
65 mmu-type:
66 description:
67 Identifies the largest MMU address translation mode supported by
68 this hart. These values originate from the RISC-V Privileged
69 Specification document, available from
70 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/string
72 enum:
73 - riscv,sv32
74 - riscv,sv39
75 - riscv,sv48
76 - riscv,sv57
77 - riscv,none
78
79 reg:
80 description:
81 The hart ID of this CPU node.
82
83 riscv,cbom-block-size:
84 $ref: /schemas/types.yaml#/definitions/uint32
85 description:
86 The blocksize in bytes for the Zicbom cache operations.
87
88 riscv,cbop-block-size:
89 $ref: /schemas/types.yaml#/definitions/uint32
90 description:
91 The blocksize in bytes for the Zicbop cache operations.
92
93 riscv,cboz-block-size:
94 $ref: /schemas/types.yaml#/definitions/uint32
95 description:
96 The blocksize in bytes for the Zicboz cache operations.
97
98 # RISC-V has multiple properties for cache op block sizes as the sizes
99 # differ between individual CBO extensions
100 cache-op-block-size: false
101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false
103
104 interrupt-controller:
105 type: object
106 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
107
108 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/phandle-array
110 items:
111 maxItems: 1
112 description: |
113 List of phandles to idle state nodes supported
114 by this hart (see ./idle-states.yaml).
115
116 capacity-dmips-mhz:
117 description:
118 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
119 DMIPS/MHz, relative to highest capacity-dmips-mhz
120 in the system.
121
122 anyOf:
123 - required:
124 - riscv,isa
125 - required:
126 - riscv,isa-base
127
128 dependencies:
129 riscv,isa-base: [ "riscv,isa-extensions" ]
130 riscv,isa-extensions: [ "riscv,isa-base" ]
131
132 required:
133 - interrupt-controller
134
135 unevaluatedProperties: false
136
137 examples:
138 - |
139 // Example 1: SiFive Freedom U540G Development Kit
140 cpus {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 timebase-frequency = <1000000>;
144 cpu@0 {
145 clock-frequency = <0>;
146 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu";
148 i-cache-block-size = <64>;
149 i-cache-sets = <128>;
150 i-cache-size = <16384>;
151 reg = <0>;
152 riscv,isa-base = "rv64i";
153 riscv,isa-extensions = "i", "m", "a", "c";
154
155 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1>;
157 compatible = "riscv,cpu-intc";
158 interrupt-controller;
159 };
160 };
161 cpu@1 {
162 clock-frequency = <0>;
163 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>;
165 d-cache-sets = <64>;
166 d-cache-size = <32768>;
167 d-tlb-sets = <1>;
168 d-tlb-size = <32>;
169 device_type = "cpu";
170 i-cache-block-size = <64>;
171 i-cache-sets = <64>;
172 i-cache-size = <32768>;
173 i-tlb-sets = <1>;
174 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39";
176 reg = <1>;
177 tlb-split;
178 riscv,isa-base = "rv64i";
179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
180
181 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1>;
183 compatible = "riscv,cpu-intc";
184 interrupt-controller;
185 };
186 };
187 };
188
189 - |
190 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 cpu@0 {
195 device_type = "cpu";
196 reg = <0>;
197 compatible = "riscv";
198 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i";
200 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
201
202 interrupt-controller {
203 #interrupt-cells = <1>;
204 interrupt-controller;
205 compatible = "riscv,cpu-intc";
206 };
207 };
208 };
209 ...
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