1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: RISC-V ISA extensions
8
9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
13
14 description: |
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions.
18 This document defines properties that indicate whether a hart supports a
19 given extension.
20
21 Once a standard extension has been ratified, no changes in behaviour can be
22 made without the creation of a new extension.
23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25 See the "i" property for more information.
26
27 select:
28 properties:
29 compatible:
30 contains:
31 const: riscv
32
33 properties:
34 riscv,isa:
35 description:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
39 https://riscv.org/specifications/
40
41 Due to revisions of the ISA specification, some deviations
42 have arisen over time.
43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
45 implies "zicntr_zicsr_zifencei_zihpm".
46
47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa string must be all
49 lowercase.
50 $ref: /schemas/types.yaml#/definitions/string
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
52 deprecated: true
53
54 riscv,isa-base:
55 description:
56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specification.
58 enum:
59 - rv32i
60 - rv64i
61
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
64 minItems: 1
65 description: Extensions supported by the hart.
66 items:
67 anyOf:
68 # single letter extensions, in canonical order
69 - const: i
70 description: |
71 The base integer instruction set, as ratified in the 20191213
72 version of the unprivileged ISA specification.
73
74 This does not include Chapter 10, "Counters", which was moved into
75 the Zicntr and Zihpm extensions after the ratification of the
76 20191213 version of the unprivileged specification.
77
78 - const: m
79 description:
80 The standard M extension for integer multiplication and division, as
81 ratified in the 20191213 version of the unprivileged ISA
82 specification.
83
84 - const: a
85 description:
86 The standard A extension for atomic instructions, as ratified in the
87 20191213 version of the unprivileged ISA specification.
88
89 - const: f
90 description:
91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version of the unprivileged ISA
93 specification.
94
95 - const: d
96 description:
97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version of the unprivileged ISA
99 specification.
100
101 - const: q
102 description:
103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version of the unprivileged ISA
105 specification.
106
107 - const: c
108 description:
109 The standard C extension for compressed instructions, as ratified in
110 the 20191213 version of the unprivileged ISA specification.
111
112 - const: v
113 description:
114 The standard V extension for vector operations, as ratified
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
117
118 - const: h
119 description:
120 The standard H extension for hypervisors as ratified in the 20191213
121 version of the privileged ISA specification.
122
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
125 description: |
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
128 changes to interrupts as frozen at commit ccbddab ("Merge pull
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130
131 - const: smstateen
132 description: |
133 The standard Smstateen extension for controlling access to CSRs
134 added by other RISC-V extensions in H/S/VS/U/VU modes and as
135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
136
137 - const: ssaia
138 description: |
139 The standard Ssaia supervisor-level extension for the advanced
140 interrupt architecture for supervisor-mode-visible csr and
141 behavioural changes to interrupts as frozen at commit ccbddab
142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
143
144 - const: sscofpmf
145 description: |
146 The standard Sscofpmf supervisor-level extension for count overflow
147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
148 to manually trigger workflow. (#2)") of riscv-count-overflow.
149
150 - const: sstc
151 description: |
152 The standard Sstc supervisor-level extension for time compare as
153 ratified at commit 3f9ed34 ("Add ability to manually trigger
154 workflow. (#2)") of riscv-time-compare.
155
156 - const: svinval
157 description:
158 The standard Svinval supervisor-level extension for fine-grained
159 address-translation cache invalidation as ratified in the 20191213
160 version of the privileged ISA specification.
161
162 - const: svnapot
163 description:
164 The standard Svnapot supervisor-level extensions for napot
165 translation contiguity as ratified in the 20191213 version of the
166 privileged ISA specification.
167
168 - const: svpbmt
169 description:
170 The standard Svpbmt supervisor-level extensions for page-based
171 memory types as ratified in the 20191213 version of the privileged
172 ISA specification.
173
174 - const: svvptc
175 description:
176 The standard Svvptc supervisor-level extension for
177 address-translation cache behaviour with respect to invalid entries
178 as ratified at commit 4a69197e5617 ("Update to ratified state") of
179 riscv-svvptc.
180
181 - const: zacas
182 description: |
183 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
184 is supported as ratified at commit 5059e0ca641c ("update to
185 ratified") of the riscv-zacas.
186
187 - const: zawrs
188 description: |
189 The Zawrs extension for entering a low-power state or for trapping
190 to a hypervisor while waiting on a store to a memory location, as
191 ratified in commit 98918c844281 ("Merge pull request #1217 from
192 riscv/zawrs") of riscv-isa-manual.
193
194 - const: zba
195 description: |
196 The standard Zba bit-manipulation extension for address generation
197 acceleration instructions as ratified at commit 6d33919 ("Merge pull
198 request #158 from hirooih/clmul-fix-loop-end-condition") of
199 riscv-bitmanip.
200
201 - const: zbb
202 description: |
203 The standard Zbb bit-manipulation extension for basic bit-manipulation
204 as ratified at commit 6d33919 ("Merge pull request #158 from
205 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
206
207 - const: zbc
208 description: |
209 The standard Zbc bit-manipulation extension for carry-less
210 multiplication as ratified at commit 6d33919 ("Merge pull request
211 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
212
213 - const: zbkb
214 description:
215 The standard Zbkb bitmanip instructions for cryptography as ratified
216 in version 1.0 of RISC-V Cryptography Extensions Volume I
217 specification.
218
219 - const: zbkc
220 description:
221 The standard Zbkc carry-less multiply instructions as ratified
222 in version 1.0 of RISC-V Cryptography Extensions Volume I
223 specification.
224
225 - const: zbkx
226 description:
227 The standard Zbkx crossbar permutation instructions as ratified
228 in version 1.0 of RISC-V Cryptography Extensions Volume I
229 specification.
230
231 - const: zbs
232 description: |
233 The standard Zbs bit-manipulation extension for single-bit
234 instructions as ratified at commit 6d33919 ("Merge pull request #158
235 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
236
237 - const: zca
238 description: |
239 The Zca extension part of Zc* standard extensions for code size
240 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
241 RV64 as it contains no instructions") of riscv-code-size-reduction,
242 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
243 of zc.adoc to src tree.").
244
245 - const: zcb
246 description: |
247 The Zcb extension part of Zc* standard extensions for code size
248 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
249 RV64 as it contains no instructions") of riscv-code-size-reduction,
250 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
251 of zc.adoc to src tree.").
252
253 - const: zcd
254 description: |
255 The Zcd extension part of Zc* standard extensions for code size
256 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
257 RV64 as it contains no instructions") of riscv-code-size-reduction,
258 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
259 of zc.adoc to src tree.").
260
261 - const: zcf
262 description: |
263 The Zcf extension part of Zc* standard extensions for code size
264 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
265 RV64 as it contains no instructions") of riscv-code-size-reduction,
266 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
267 of zc.adoc to src tree.").
268
269 - const: zcmop
270 description:
271 The standard Zcmop extension version 1.0, as ratified in commit
272 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
273
274 - const: zfa
275 description:
276 The standard Zfa extension for additional floating point
277 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
278 riscv-isa-manual.
279
280 - const: zfh
281 description:
282 The standard Zfh extension for 16-bit half-precision binary
283 floating-point instructions, as ratified in commit 64074bc ("Update
284 version numbers for Zfh/Zfinx") of riscv-isa-manual.
285
286 - const: zfhmin
287 description:
288 The standard Zfhmin extension which provides minimal support for
289 16-bit half-precision binary floating-point instructions, as ratified
290 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
291 riscv-isa-manual.
292
293 - const: zk
294 description:
295 The standard Zk Standard Scalar cryptography extension as ratified
296 in version 1.0 of RISC-V Cryptography Extensions Volume I
297 specification.
298
299 - const: zkn
300 description:
301 The standard Zkn NIST algorithm suite extensions as ratified in
302 version 1.0 of RISC-V Cryptography Extensions Volume I
303 specification.
304
305 - const: zknd
306 description: |
307 The standard Zknd for NIST suite: AES decryption instructions as
308 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
309 specification.
310
311 - const: zkne
312 description: |
313 The standard Zkne for NIST suite: AES encryption instructions as
314 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
315 specification.
316
317 - const: zknh
318 description: |
319 The standard Zknh for NIST suite: hash function instructions as
320 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
321 specification.
322
323 - const: zkr
324 description:
325 The standard Zkr entropy source extension as ratified in version
326 1.0 of RISC-V Cryptography Extensions Volume I specification.
327 This string being present means that the CSR associated to this
328 extension is accessible at the privilege level to which that
329 device-tree has been provided.
330
331 - const: zks
332 description:
333 The standard Zks ShangMi algorithm suite extensions as ratified in
334 version 1.0 of RISC-V Cryptography Extensions Volume I
335 specification.
336
337 - const: zksed
338 description: |
339 The standard Zksed for ShangMi suite: SM4 block cipher instructions
340 as ratified in version 1.0 of RISC-V Cryptography Extensions
341 Volume I specification.
342
343 - const: zksh
344 description: |
345 The standard Zksh for ShangMi suite: SM3 hash function instructions
346 as ratified in version 1.0 of RISC-V Cryptography Extensions
347 Volume I specification.
348
349 - const: zkt
350 description:
351 The standard Zkt for data independent execution latency as ratified
352 in version 1.0 of RISC-V Cryptography Extensions Volume I
353 specification.
354
355 - const: zicbom
356 description:
357 The standard Zicbom extension for base cache management operations as
358 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
359
360 - const: zicbop
361 description:
362 The standard Zicbop extension for cache-block prefetch instructions
363 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
364 riscv-CMOs.
365
366 - const: zicboz
367 description:
368 The standard Zicboz extension for cache-block zeroing as ratified
369 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
370
371 - const: zicntr
372 description:
373 The standard Zicntr extension for base counters and timers, as
374 ratified in the 20191213 version of the unprivileged ISA
375 specification.
376
377 - const: zicond
378 description:
379 The standard Zicond extension for conditional arithmetic and
380 conditional-select/move operations as ratified in commit 95cf1f9
381 ("Add changes requested by Ved during signoff") of riscv-zicond.
382
383 - const: zicsr
384 description: |
385 The standard Zicsr extension for control and status register
386 instructions, as ratified in the 20191213 version of the
387 unprivileged ISA specification.
388
389 This does not include Chapter 10, "Counters", which documents
390 special case read-only CSRs, that were moved into the Zicntr and
391 Zihpm extensions after the ratification of the 20191213 version of
392 the unprivileged specification.
393
394 - const: zifencei
395 description:
396 The standard Zifencei extension for instruction-fetch fence, as
397 ratified in the 20191213 version of the unprivileged ISA
398 specification.
399
400 - const: zihintpause
401 description:
402 The standard Zihintpause extension for pause hints, as ratified in
403 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
404
405 - const: zihintntl
406 description:
407 The standard Zihintntl extension for non-temporal locality hints, as
408 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
409 riscv-isa-manual.
410
411 - const: zihpm
412 description:
413 The standard Zihpm extension for hardware performance counters, as
414 ratified in the 20191213 version of the unprivileged ISA
415 specification.
416
417 - const: zimop
418 description:
419 The standard Zimop extension version 1.0, as ratified in commit
420 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
421
422 - const: ztso
423 description:
424 The standard Ztso extension for total store ordering, as ratified
425 in commit 2e5236 ("Ztso is now ratified.") of the
426 riscv-isa-manual.
427
428 - const: zvbb
429 description:
430 The standard Zvbb extension for vectored basic bit-manipulation
431 instructions, as ratified in commit 56ed795 ("Update
432 riscv-crypto-spec-vector.adoc") of riscv-crypto.
433
434 - const: zvbc
435 description:
436 The standard Zvbc extension for vectored carryless multiplication
437 instructions, as ratified in commit 56ed795 ("Update
438 riscv-crypto-spec-vector.adoc") of riscv-crypto.
439
440 - const: zve32f
441 description:
442 The standard Zve32f extension for embedded processors, as ratified
443 in commit 6f702a2 ("Vector extensions are now ratified") of
444 riscv-v-spec.
445
446 - const: zve32x
447 description:
448 The standard Zve32x extension for embedded processors, as ratified
449 in commit 6f702a2 ("Vector extensions are now ratified") of
450 riscv-v-spec.
451
452 - const: zve64d
453 description:
454 The standard Zve64d extension for embedded processors, as ratified
455 in commit 6f702a2 ("Vector extensions are now ratified") of
456 riscv-v-spec.
457
458 - const: zve64f
459 description:
460 The standard Zve64f extension for embedded processors, as ratified
461 in commit 6f702a2 ("Vector extensions are now ratified") of
462 riscv-v-spec.
463
464 - const: zve64x
465 description:
466 The standard Zve64x extension for embedded processors, as ratified
467 in commit 6f702a2 ("Vector extensions are now ratified") of
468 riscv-v-spec.
469
470 - const: zvfh
471 description:
472 The standard Zvfh extension for vectored half-precision
473 floating-point instructions, as ratified in commit e2ccd05
474 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
475
476 - const: zvfhmin
477 description:
478 The standard Zvfhmin extension for vectored minimal half-precision
479 floating-point instructions, as ratified in commit e2ccd05
480 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
481
482 - const: zvkb
483 description:
484 The standard Zvkb extension for vector cryptography bit-manipulation
485 instructions, as ratified in commit 56ed795 ("Update
486 riscv-crypto-spec-vector.adoc") of riscv-crypto.
487
488 - const: zvkg
489 description:
490 The standard Zvkg extension for vector GCM/GMAC instructions, as
491 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
492 of riscv-crypto.
493
494 - const: zvkn
495 description:
496 The standard Zvkn extension for NIST algorithm suite instructions, as
497 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
498 of riscv-crypto.
499
500 - const: zvknc
501 description:
502 The standard Zvknc extension for NIST algorithm suite with carryless
503 multiply instructions, as ratified in commit 56ed795 ("Update
504 riscv-crypto-spec-vector.adoc") of riscv-crypto.
505
506 - const: zvkned
507 description:
508 The standard Zvkned extension for Vector AES block cipher
509 instructions, as ratified in commit 56ed795 ("Update
510 riscv-crypto-spec-vector.adoc") of riscv-crypto.
511
512 - const: zvkng
513 description:
514 The standard Zvkng extension for NIST algorithm suite with GCM
515 instructions, as ratified in commit 56ed795 ("Update
516 riscv-crypto-spec-vector.adoc") of riscv-crypto.
517
518 - const: zvknha
519 description: |
520 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
521 hash (SHA-256 only) instructions, as ratified in commit
522 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
523
524 - const: zvknhb
525 description: |
526 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
527 hash (SHA-256 and SHA-512) instructions, as ratified in commit
528 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
529
530 - const: zvks
531 description:
532 The standard Zvks extension for ShangMi algorithm suite
533 instructions, as ratified in commit 56ed795 ("Update
534 riscv-crypto-spec-vector.adoc") of riscv-crypto.
535
536 - const: zvksc
537 description:
538 The standard Zvksc extension for ShangMi algorithm suite with
539 carryless multiplication instructions, as ratified in commit 56ed795
540 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
541
542 - const: zvksed
543 description: |
544 The standard Zvksed extension for ShangMi suite: SM4 block cipher
545 instructions, as ratified in commit 56ed795 ("Update
546 riscv-crypto-spec-vector.adoc") of riscv-crypto.
547
548 - const: zvksh
549 description: |
550 The standard Zvksh extension for ShangMi suite: SM3 secure hash
551 instructions, as ratified in commit 56ed795 ("Update
552 riscv-crypto-spec-vector.adoc") of riscv-crypto.
553
554 - const: zvksg
555 description:
556 The standard Zvksg extension for ShangMi algorithm suite with GCM
557 instructions, as ratified in commit 56ed795 ("Update
558 riscv-crypto-spec-vector.adoc") of riscv-crypto.
559
560 - const: zvkt
561 description:
562 The standard Zvkt extension for vector data-independent execution
563 latency, as ratified in commit 56ed795 ("Update
564 riscv-crypto-spec-vector.adoc") of riscv-crypto.
565
566 - const: xandespmu
567 description:
568 The Andes Technology performance monitor extension for counter overflow
569 and privilege mode filtering. For more details, see Counter Related
570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
572
573 allOf:
574 # Zcb depends on Zca
575 - if:
576 contains:
577 const: zcb
578 then:
579 contains:
580 const: zca
581 # Zcd depends on Zca and D
582 - if:
583 contains:
584 const: zcd
585 then:
586 allOf:
587 - contains:
588 const: zca
589 - contains:
590 const: d
591 # Zcf depends on Zca and F
592 - if:
593 contains:
594 const: zcf
595 then:
596 allOf:
597 - contains:
598 const: zca
599 - contains:
600 const: f
601 # Zcmop depends on Zca
602 - if:
603 contains:
604 const: zcmop
605 then:
606 contains:
607 const: zca
608
609 allOf:
610 # Zcf extension does not exist on rv64
611 - if:
612 properties:
613 riscv,isa-extensions:
614 contains:
615 const: zcf
616 riscv,isa-base:
617 contains:
618 const: rv64i
619 then:
620 properties:
621 riscv,isa-extensions:
622 not:
623 contains:
624 const: zcf
625
626 additionalProperties: true
627 ...
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