1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Cadence UART Controller
8
9 maintainers:
10 - Michal Simek <michal.simek@amd.com>
11
12 properties:
13 compatible:
14 oneOf:
15 - description: UART controller for Zynq-7xxx SoC
16 items:
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
20 items:
21 - const: xlnx,zynqmp-uart
22 - const: cdns,uart-r1p12
23
24 reg:
25 maxItems: 1
26
27 interrupts:
28 maxItems: 1
29
30 clocks:
31 maxItems: 2
32
33 clock-names:
34 items:
35 - const: uart_clk
36 - const: pclk
37
38 cts-override:
39 description: |
40 Override the CTS modem status signal. This signal will
41 always be reported as active instead of being obtained
42 from the modem status register. Define this if your serial
43 port does not use this pin.
44 type: boolean
45
46 power-domains:
47 maxItems: 1
48
49 resets:
50 maxItems: 1
51
52 required:
53 - compatible
54 - reg
55 - interrupts
56 - clocks
57 - clock-names
58
59 allOf:
60 - $ref: serial.yaml#
61 - $ref: rs485.yaml#
62 - if:
63 properties:
64 compatible:
65 contains:
66 const: cdns,uart-r1p8
67 then:
68 properties:
69 power-domains: false
70
71 unevaluatedProperties: false
72
73 examples:
74 - |
75 uart0: serial@e0000000 {
76 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
77 clocks = <&clkc 23>, <&clkc 40>;
78 clock-names = "uart_clk", "pclk";
79 reg = <0xe0000000 0x1000>;
80 interrupts = <0 27 4>;
81 };
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