1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Geni based QUP UART interface
8
9 maintainers:
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12
13 allOf:
14 - $ref: /schemas/serial/serial.yaml#
15
16 properties:
17 compatible:
18 enum:
19 - qcom,geni-uart
20 - qcom,geni-debug-uart
21
22 clocks:
23 maxItems: 1
24
25 clock-names:
26 const: se
27
28 interconnects:
29 maxItems: 2
30
31 interconnect-names:
32 items:
33 - const: qup-core
34 - const: qup-config
35
36 interrupts:
37 minItems: 1
38 items:
39 - description: UART core irq
40 - description: Wakeup irq (RX GPIO)
41
42 operating-points-v2: true
43
44 pinctrl-0: true
45 pinctrl-1: true
46
47 pinctrl-names:
48 minItems: 1
49 items:
50 - const: default
51 - const: sleep
52
53 power-domains:
54 maxItems: 1
55
56 reg:
57 maxItems: 1
58
59 required:
60 - compatible
61 - clocks
62 - clock-names
63 - interrupts
64 - reg
65
66 unevaluatedProperties: false
67
68 examples:
69 - |
70 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
72 #include <dt-bindings/interconnect/qcom,sc7180.h>
73
74 serial@a88000 {
75 compatible = "qcom,geni-uart";
76 reg = <0xa88000 0x7000>;
77 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
78 clock-names = "se";
79 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
80 pinctrl-0 = <&qup_uart0_default>;
81 pinctrl-names = "default";
82 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
83 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
84 interconnect-names = "qup-core", "qup-config";
85 };
86 ...
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