1 * Parallel I/O Ports
2
3 This node configures Parallel I/O ports for CPUs with QE support.
4 The node should reside in the "soc" node of the tree. For each
5 device that using parallel I/O ports, a child node should be created.
6 See the definition of the Pin configuration nodes below for more
7 information.
8
9 Required properties:
10 - device_type : should be "par_io".
11 - reg : offset to the register set and its length.
12 - num-ports : number of Parallel I/O ports
13
14 Example:
15 par_io@1400 {
16 reg = <1400 100>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 device_type = "par_io";
20 num-ports = <7>;
21 ucc_pin@1 {
22 ......
23 };
24
25 Note that "par_io" nodes are obsolete, and should not be used for
26 the new device trees. Instead, each Par I/O bank should be represented
27 via its own gpio-controller node:
28
29 Required properties:
30 - #gpio-cells : should be "2".
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
33 - reg : offset to the register set and its length.
34 - gpio-controller : node to identify gpio controllers.
35
36 Example:
37 qe_pio_a: gpio-controller@1400 {
38 #gpio-cells = <2>;
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
41 reg = <0x1400 0x18>;
42 gpio-controller;
43 };
44
45 qe_pio_e: gpio-controller@1460 {
46 #gpio-cells = <2>;
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
49 reg = <0x1460 0x18>;
50 gpio-controller;
51 };
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