1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ANATOP register
8
9 maintainers:
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12
13 properties:
14 compatible:
15 oneOf:
16 - items:
17 - enum:
18 - fsl,imx6sl-anatop
19 - fsl,imx6sll-anatop
20 - fsl,imx6sx-anatop
21 - fsl,imx6ul-anatop
22 - fsl,imx7d-anatop
23 - const: fsl,imx6q-anatop
24 - const: syscon
25 - const: simple-mfd
26 - items:
27 - const: fsl,imx6q-anatop
28 - const: syscon
29 - const: simple-mfd
30
31 reg:
32 maxItems: 1
33
34 interrupts:
35 items:
36 - description: Temperature sensor event
37 - description: Brown-out event on either of the support regulators
38 - description: Brown-out event on either the core, gpu or soc regulators
39
40 tempmon:
41 type: object
42 unevaluatedProperties: false
43 $ref: /schemas/thermal/imx-thermal.yaml
44
45 patternProperties:
46 "regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$":
47 type: object
48 unevaluatedProperties: false
49 $ref: /schemas/regulator/anatop-regulator.yaml
50
51 required:
52 - compatible
53 - reg
54
55 additionalProperties: false
56
57 examples:
58 - |
59 #include <dt-bindings/clock/imx6ul-clock.h>
60 #include <dt-bindings/interrupt-controller/arm-gic.h>
61
62 anatop: anatop@20c8000 {
63 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
64 "syscon", "simple-mfd";
65 reg = <0x020c8000 0x1000>;
66 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
69
70 reg_3p0: regulator-3p0 {
71 compatible = "fsl,anatop-regulator";
72 regulator-name = "vdd3p0";
73 regulator-min-microvolt = <2625000>;
74 regulator-max-microvolt = <3400000>;
75 anatop-reg-offset = <0x120>;
76 anatop-vol-bit-shift = <8>;
77 anatop-vol-bit-width = <5>;
78 anatop-min-bit-val = <0>;
79 anatop-min-voltage = <2625000>;
80 anatop-max-voltage = <3400000>;
81 anatop-enable-bit = <0>;
82 };
83
84 reg_arm: regulator-vddcore {
85 compatible = "fsl,anatop-regulator";
86 regulator-name = "cpu";
87 regulator-min-microvolt = <725000>;
88 regulator-max-microvolt = <1450000>;
89 regulator-always-on;
90 anatop-reg-offset = <0x140>;
91 anatop-vol-bit-shift = <0>;
92 anatop-vol-bit-width = <5>;
93 anatop-delay-reg-offset = <0x170>;
94 anatop-delay-bit-shift = <24>;
95 anatop-delay-bit-width = <2>;
96 anatop-min-bit-val = <1>;
97 anatop-min-voltage = <725000>;
98 anatop-max-voltage = <1450000>;
99 };
100
101 reg_soc: regulator-vddsoc {
102 compatible = "fsl,anatop-regulator";
103 regulator-name = "vddsoc";
104 regulator-min-microvolt = <725000>;
105 regulator-max-microvolt = <1450000>;
106 regulator-always-on;
107 anatop-reg-offset = <0x140>;
108 anatop-vol-bit-shift = <18>;
109 anatop-vol-bit-width = <5>;
110 anatop-delay-reg-offset = <0x170>;
111 anatop-delay-bit-shift = <28>;
112 anatop-delay-bit-width = <2>;
113 anatop-min-bit-val = <1>;
114 anatop-min-voltage = <725000>;
115 anatop-max-voltage = <1450000>;
116 };
117
118 tempmon: tempmon {
119 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
120 interrupt-parent = <&gpc>;
121 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
122 fsl,tempmon = <&anatop>;
123 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
124 nvmem-cell-names = "calib", "temp_grade";
125 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
126 #thermal-sensor-cells = <0>;
127 };
128 };
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