1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Always-On Subsystem side channel
8
9 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12 description:
13 This binding describes the hardware component responsible for side channel
14 requests to the always-on subsystem (AOSS), used for certain power management
15 requests that is not handled by the standard RPMh interface. Each client in the
16 SoC has its own block of message RAM and IRQ for communication with the AOSS.
17 The protocol used to communicate in the message RAM is known as Qualcomm
18 Messaging Protocol (QMP)
19
20 The AOSS side channel exposes control over a set of resources, used to control
21 a set of debug related clocks and to affect the low power state of resources
22 related to the secondary subsystems.
23
24 properties:
25 compatible:
26 items:
27 - enum:
28 - qcom,qdu1000-aoss-qmp
29 - qcom,sa8775p-aoss-qmp
30 - qcom,sc7180-aoss-qmp
31 - qcom,sc7280-aoss-qmp
32 - qcom,sc8180x-aoss-qmp
33 - qcom,sc8280xp-aoss-qmp
34 - qcom,sdx75-aoss-qmp
35 - qcom,sdm845-aoss-qmp
36 - qcom,sm6350-aoss-qmp
37 - qcom,sm8150-aoss-qmp
38 - qcom,sm8250-aoss-qmp
39 - qcom,sm8350-aoss-qmp
40 - qcom,sm8450-aoss-qmp
41 - qcom,sm8550-aoss-qmp
42 - qcom,sm8650-aoss-qmp
43 - qcom,x1e80100-aoss-qmp
44 - const: qcom,aoss-qmp
45
46 reg:
47 maxItems: 1
48 description:
49 The base address and size of the message RAM for this client's
50 communication with the AOSS
51
52 interrupts:
53 maxItems: 1
54 description:
55 Should specify the AOSS message IRQ for this client
56
57 mboxes:
58 maxItems: 1
59 description:
60 Reference to the mailbox representing the outgoing doorbell in APCS for
61 this client, as described in mailbox/mailbox.txt
62
63 "#clock-cells":
64 const: 0
65 description:
66 The single clock represents the QDSS clock.
67
68 required:
69 - compatible
70 - reg
71 - interrupts
72 - mboxes
73 - "#clock-cells"
74
75 additionalProperties: false
76
77 patternProperties:
78 "^(cx|mx|ebi)$":
79 type: object
80 description:
81 The AOSS side channel also provides the controls for three cooling devices,
82 these are expressed as subnodes of the QMP node. The name of the node is
83 used to identify the resource and must therefore be "cx", "mx" or "ebi".
84
85 properties:
86 "#cooling-cells":
87 const: 2
88
89 required:
90 - "#cooling-cells"
91
92 additionalProperties: false
93
94 examples:
95 - |
96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97
98 aoss_qmp: qmp@c300000 {
99 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
100 reg = <0x0c300000 0x100000>;
101 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
102 mboxes = <&apss_shared 0>;
103
104 #clock-cells = <0>;
105
106 cx_cdev: cx {
107 #cooling-cells = <2>;
108 };
109
110 mx_cdev: mx {
111 #cooling-cells = <2>;
112 };
113 };
114 ...
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